1. 1 SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects Qiang Xu and Yubin Zhang Krishnendu Chakrabarty The Chinese University of Hong KongDuke University

2. 2 Outline  1 Background  2 Motivation  3 Two-D SI test set compaction  4 SOC test architecture optimization  5 Experimental results  6 Conclusion

3. 3 Signal Integrity

4. 4 Signal integrity Signal integrity is a major concern!

5. 5 Behavioral Interconnect SI Fault Models  Maximal aggressor (MA) model (Cuviello ICCAD ’ 99) All aggressors make the same simultaneous transition in the same direction Victim stay quiescent or makes an opposite transition 6N test vector pairs for N interconnects  Multiple transition (MT) model (Tehranipour TCAD ’ 04) Covers all transitions on victim and multiple transitions on aggressors Exploit locality to reduce test pattern count – roughly test vector pairs

6. 6 BIST for Interconnect SI Test?  May cause over-testing or under-testing  Hard to work for arbitrary SOC topology Test stimuli loaded from external tester

7. 7 Wrapper Cells for Interconnect SI Test  Provide consecutive transitions at driving side  Embed integrity loss sensor at receiving side (e.g., Bai DAC ’ 00; Tehranipour TCAD ’ 04)

8. 8 SOC Test Architecture Design  Objective: solve the test access problem Test Bus Architecture TestRail Architecture

9. 9 SOC Test Architecture Optimization  Objective: Minimize Testing Time. Wrapper design and optimization TAM width for each core Test scheduling  NP-hard Problem  Many Contributions Integer linear programming (ILP) [Jetta ’ 02] Rectangle packing algorithm [ATS ’ 01] TR-Architect algorithm [ITC ’ 02] Lagrange-based algorithm [DAC ’ 03] Graph-based algorithm [Jetta ’ 04] … Prior work focuses on core internal test only!

10. 10 Importance of Interconnect SI Test  SI test pattern count can be large Take 32-bit bus with 10 cores as an example  Victim interconnect number N=2*10*32=640 (Assume each core sends data to two other cores)  2560 test vector pairs for MA model  163840 test vector pairs for MT model with k=3  SI test using serial external test is expensive Millions of clock cycles for MA model Two orders higher for MT model

11. 11 Observation and Motivation  Victim is typically affected by a few nearby aggressors only Test pattern features lots of don ’ t-care bits Effective compaction strategy  Parallel external test should be used to reduce interconnect SI testing time TestRail architecture  SOC test architecture needs to be optimized to reduce the total time of both core tests and interconnect tests

12. 12 SOC Test Architecture for SI Faults

13. 13 Interconnect SI Test Pattern Format Core-1 WOC Core-2 WOC Core-3 WOC …Core-n WOC Bus P1...↑x↓xxxxx…0xx…↑…xx↑…xx1… P2…xxxxxx↑x…xx↓…x…↓xx…xx1… P3…x↑xx↓x↓x…xxx…x…xxx… P4…xxxx↑xxx…↓xx…x…x↓x…1xx… P5...↑x↓xx1xx…xxx…↑…↑xx…xxx… ……

14. 14 Vertical Dimension Compaction (Pattern Count Reduction)  Graph approch Vertex  Pattern; Edge  Compatibility Maximum clique partitioning produce minimum number of compacted test pattern sets High computational time  Greedy heuristic Start from the first pattern and merge with the following compatible patterns Low computational time Quality depends on pattern order  Randomize it and do multiple times 1 53 4 2

15. 15 Interconnect SI test pattern format Core-1 WOC Core-2 WOC Core-3 WOC …Core-n WOC Bus P1...↑x↓xxxxx…0xx…↑…xx↑…xx1… P2…xxxxxx↑x…xx↓…x…↓xx…xx1… P3…x↑xx ↓ x↓x…xxx…x…xxx… P4…xxxx↑xxx…↓xx…x…x↓x…1xx… P5...↑x↓xx1xx…xxx…↑…↑xx…xxx… ……

16. 16 Horizontal Dimension Compaction (Pattern Length Reduction)  Motivation Each test pattern involves only a few cores ’ terminals  Approach Bypass the boundaries of those uninvolved cores  cores grouping Tradeoff between control circuit complexity and test pattern length reduction

17. 17 Horizontal Dimension Compaction (Pattern Length Reduction) – Cont.  Creating hypergraph Vertex  Core  Vertex weight  Number of core ’ s WOCs Hyper-edge  Cores involved in a test pattern  Edge weight  Number of times  Hypergraph partition Goal: Minimum cut Tool: hMetis 1 2 7 3 4 6 5

18. 18 Problem Formulation  Given Maximum TAM width W max Test set parameters for each core Test set parameters for each group of compacted SI test sets  Determine Wrapper design for each core TAM resource assigned to each core Test schedule for entire SOC Goal: Minimize total SOC testing time!

19. 19 Impact of TAM Architecture on SI Testing Time

20. 20 Complexity of SI Test  Core testing time related to TAM width only Can be pre-computed  Interconnect SI testing time involves multiple TAMs Cannot be computed until TAM architecture is known

21. 21 SOC Test Architecture Optimization for Interconnect SI Faults Construct an initial TAM design Modified TR-Architect optimization Schedule SI Tests Satisfied? No

22. 22 TR-Architect Optimization Source: Goel and Marinissen ITC’02

23. 23 TR-Architect Optimization – Cont. Source: Goel and Marinissen ITC’02

24. 24 What’s Different?  There may be multiple bottleneck TAMs Redefine bottleneck TAMs as TAMs, when assigned extra TAM wires, may reduce SOC total testing time

25. 25 What’s Different? – Cont.  How to identify bottleneck TAMs? Search core internal test and all SI tests  How to merge TAMs and distribute free TAM wires? Try all candidates and select the best one  How to schedule SI tests? Rectangle packing

26. 26 Experimental Setup  Random test pattern 1 victim and N a (2~6) aggressors At most 2 of N a are out of the victim cores 32 bits bus P (bus is occupied) = 50% 1~N a bus bits are used if bus is occupied

27. 27 Experiment Result for 2-D SI Test Set Compaction (SOC p93791) Ng Nr = 10,000Nr = 100,000 NcDs∆Ds(%)NcDs∆Ds (%) 12712885879/246826281732/ 22932507958-13.10257722102780-15.90 43102222363-22.99257619651865-25.23 83312119383-26.56269018863425-28.23

28. 28 Experiment Results for Test Architecture Optimization (p93791, N r = 10,000) W max T [8] T g1 T g2 T g4 T g8 T min ∆ T [8] (%) ∆ T g (%) 8 422688441796553979541406675140549773979541-5.85-4.79 16 219188120739792056323203433720364162034337-7.19-1.91 24 215086514131211373548137075113915131370751-36.27-3.00 32 10765161040041105066910616501026305 -4.66-1.32 40 1016416841403838764824816829521824816-18.85-1.97 48 1212780708625702850696281737059696281-42.59-1.74 56 853904606648606572594544604312594544-30.37-2.00 64 784973528843539587521242520286 -33.72-1.62

29. 29 Experiment Results for Test Architecture Optimization (p93791, N r = 100,000) W max T [8] T g1 T g2 T g4 T g8 T min ∆ T [8] (%) ∆ T g (%) 8 92799847157553662933364825376308163 -32.02-11.87 16 49359343650655338286432311373170750 -35.76-13.15 24 95327852459100225825321906332187138 -77.06-11.06 32 21772131882999173200016681091650127 -24.21-12.37 40 28794721523711142258613515911338896 -53.50-12.13 48 59692851256464117639011697941160866 -80.55-7.61 56 347931910716981008224995447985120 -71.69-8.08 64 3410388923350856743848786867541848786-75.11-8.08

30. 30 Summary  Motivation SI test becomes more important with shrinking technology feature size Prior work focus on core internal test only  Contribution 2-D test pattern compaction strategy SOC test architecture optimization algorithm  Result Significantly reduce total SOC test time  Future Work Improved test compaction algorithm Mixed InTest & ExTest scheduling algorithm