1. [1] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 POLYMER ON CHIP Under the guidance of Mr. Vivek Sharma Advisor Submitted by Dillip Kumar Konhar EI200127183

2. [2] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 INTRODUCTION  Aim of improving microelectronics chip.  Lower cost,increase the packing density (size)improve performance and reliability.  Polymer-chip process where the semiconductor chip is assembled face down onto circuit board is ideal for size.why?  There is no extra area needed for contacting on the sides of component.  Performance is superior because length of connection is minimized.

3. [3] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 A Wafer arrives from IC mfr tested Pick and place Polymer chip Add flux to substrate Dicing Place on t a pe reel Or wafer pack l ReflowClean Underfill CompleteUnderfill cure Bumping SOLDERING PROCESS

4. [4] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 POLYMER CHIP PROCESS  By soldering joining  By thermocompression  Thermosonic joining

5. [5] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 POLYMER CHIP JOINING BY USING ADHESIVES  Isotropic adhesive  Anisotropic adhesive  Nonconductive adhesive

6. [6] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 DIFFERENT TYPES OF JOINTS

7. [7] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 DISADVANTAGES  Repairing is difficult or impossible.  Handling of bare chips is difficult.  Difficult testing of bare dies.  Limited availability of bumped chip.  High assembly accuracy needed.  Material underfilling with curing time is needed.

8. [8] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 ADVANTAGES. Ieds  Smaller size  Increased functionality  Improved performance  Improved thermal capabilities  Improved reliability  Low cost

9. [9] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 FABRICATION  Polymer pillars fabricated directly on semiconductor chip  Integrated with passive devices  Radius and length are illuminated  30nm Ti and 700nm Au layers in photolithography pattern.  Center-to-center spacing is 325 m  Thin silicon nitride deposited.

10. [10] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 Relative cost comparison  Bumping cost.  Assembly process cost.  Die bumping cost.  Cost of substrate. Availability of components  Bumped chip or bare die.  Soldering bump.  Synthetic flavours.  Synthetic microfibers.  Composite materials.

11. [11] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 SMART MATERIALS  Shape memory alloys.  Liquid crystal in coated fabrics.  Thermochronic dyes.  Modified starches.  Cellular carbon and kevlar.  Teflon.

12. [12] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 MODERN MATERIALS FOR POLYMER  Polycapralactone.  Lenticullar sheet.  Shape memory alloy (SMA).  Thermochronic film.

13. [13] National Institute of Science & Technology TECHNICAL SEMINAR PRESENTATION DILLIP KUMAR KONHAR EI200127183 CONCLUSION  Polymer chip based devise coupled to the API 3000 mass spectrometer.  The device can be used for proteomic research.  Characteristic of PDs do not degrade in fabrication.  Future fabrication can be done both electrical and optical polymer.  Lateral compliance minimizes optical losses due to offset and enhanced chip reliability. THANK YOU !!