1. Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 Short Talk Optimal Designs of CMOS Circuits via Geometric Programming Yu-Shun Wang Dec. 27 th 2007

2. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所Outline  Introduction  Convex Optimizing  Geometric Form  GP solver  Applications  RFIC - LNA  Operating Amplifier  Adder  Future Challenge 2

3. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 3 Thinking  When a designer has a good idea, a new topology or a new design theory will be born in few days. But the designer has to tune all performance well for weeks.  Including parasitic resistors and capacitors, the performance won’t be predictable easily. So the ineffective fine tune will take 80% effort in a circuit.  If unfortunately, the idea doesn’t work…and time goes by.  So a good automatic optimization EDA tool is necessary. New Idea Well Design Compared with Design Goal Deciding Topology Handy Calculation Fine Tune !!

4. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 4 Advantages 1.A lot of develop time can be saved. 2.We can change specification easily. 3.By only updating the transistor data, we can port a design to a new process immediately. 4.Geometric programming encapsulates the experienced designer’s knowledge.

5. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所Outline  Introduction  Convex Optimizing  Geometric Form  GP solver  Applications  Operating Amplifier  LNA  Adder  Future Challenge 5

6. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 6 Fundamental Concept  Convex form

7. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 Fundamental Concept  Quasi convex function 7

8. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所  Convex standard From where, are convex functions. Fundamental Concept 8 Minimize Subject to

9. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 9 Geometric Programming  Geometric Program Standard From A geometric program is an optimization problem where are posynomial function, and are monomial function.  Convex Form ? Minimize Subject to

10. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 10 Geometric Programming  How can Geometric Program be Solved To convert geometric program to convex optimization Assume,we minimize,then Minimize Subject to

11. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 11 Geometric Programming  How can Geometric Program be Solved Therefore, if Under the transformation, it becomes Assume,then for any y, and any with, then Geometric Program can convert to convex standard form. In term of original posynominal f, the convex form is following  Posynomial !!

12. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所Outline  Introduction  Convex Optimizing  Geometric Form  GP solver  Applications  RFIC - LNA  Operating Amplifier  Adder  Future Challenge 12

13. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 GP solver 1.Define target (Min or Max something) 2.Define constraint 3.http://www.stanford.edu/~boyd/ggplab/http://www.stanford.edu/~boyd/ggplab/ 4.Rewrite formula in matrix format 5.Feed Matlab with matrix.m 13

14. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 GP solver 14 matrix.m Matlab.mat

15. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 GP solver 15 Assign variable Constraint matrix Call function Rewrite performance Objective matrix

16. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 GP solver 16 Rewrite performance iterations Solved results

17. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所Outline  Introduction  Convex Optimizing  Geometric Form  GP solver  Applications  RFIC – LNA  Operating Amplifier  Adder  Future Challenge 17

18. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 18 RFIC - LNA

19. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 19 Low Noise Amplifier (LNA)  RF Circuits using Geometric Programming 1.Input Impedance 2.S-parameter (S 11 、 S 21, 、 S 12 、 S 22 ) 3.NF (Noise Figure) Posynomial !! Signomial -> Posynomial !!

20. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 20 LNA

21. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 21 LNA

22. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 22 Experience Result TargetOptimize Technology － 0.18-μm CMOS Frequency2.4 W1W1 >0.40.4 L1L1 >0.180.397 Supply Voltage33 Power Dissipationminimum7.56 S 21 >2323 S 11 =-∞-355

23. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所Outline  Introduction  Convex Optimizing  Geometric Form  GP solver  Applications  RFIC - LNA  Operating Amplifier  Adder  Future Challenge 23

24. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所  Maria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee, “Optimal Design of a CMOS Op-Amp via Geometric Program­ming,” IEEE Transactions on Computer-aided Design of Inte­grated Circuits and Systems, vol. 20, no. 1, Jan. 2001. 24 2-Stage Operating Amplifier Output Input+ Input-

25. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 Small Signal Model 25

26. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 Small Signal Model 26

27. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所  First performance: Gain 27 2-Stage Operating Amplifier

28. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所  Second performance: Pole 28 2-Stage Operating Amplifier

29. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 29 Geometric Programming  Performance Formula Posynomial !! Inverse Posynomial !!

30. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 30 Optimization of OP-Amp

31. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 31 Optimization of OP-Amp  Constraint Maximize Chip size Subject to

32. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 32 Constraint

33. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 33 Experience Result Unit target Optimized Technology － － 0.8-μm CMOS W1W1 um >0.8 0.8 W2W2 um >0.8 0.8 W3W3 um >0.8 43 W4W4 um >0.8 43 W5W5 um >0.8 0.8 W6W6 um >0.8 86 W7W7 um >0.8 0.8 L1L1 um >2 2 L2L2 um >2 2 L3L3 um >2 2 L4L4 um >2 2 L5L5 um >2 344 L6L6 um >2 1.6 L7L7 um >2 344 Supply VoltageV 3 3 Chip Size um 2 minimum 836 Power DissipationmW <50 50 Open loop gaindB >80 80

34. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 34 Optimal Design Result

35. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所  Ignore some factor…  body effect  channel length modulation  junction capacitance…. Caparison with real model 35

36. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 Fit the nonlinear model  Rewrite gm 36

37. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所Limitation  Accuracy model ?  GP0  Hspice level-1  GP1  Hspice level-39 ( 0.8um CMOS Bsim 3v1)  ??  90nm CMOS Bsim 3v3…….. 37

38. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所Outline  Introduction  Convex Optimizing  Geometric Form  GP solver  Applications  RFIC - LNA  Operating Amplifier  Adder  Future Challenge 38

39. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 HCA radix-2 Architecture Generate even carries using radix-2 (P,G) Generate odd carries from even carries CMOS adder for sum 1-b cell width  4  m 10-stage critical path 39

40. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 KS radix-4 Architecture 40

41. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 Novel Architecture Gather all critical path KS Radix - 2 41

42. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 Critical Path Problem  How to synchronize all path?  Use GP !! (Transistor sizing) 42 16 24 32

43. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所  Minimize critical path’s delay time by increase device width Solved by Geometric Program  Minimize all device’s widths by synchronizing critical path delay time to get low power consumption 43

44. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 1: Delay Time Model 44 Process-depend parameter Target variable Assign variable

45. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 2: Minimize Delay Time 45

46. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 2: Minimize Delay Time 46 Optimized Ws Minimized Delay time 3pF

47. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 2: Minimize Delay Time 47 Optimized Ws Minimized Delay time 0.1 3pF6pF

48. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 3: Minimize Ws 48  Minimize all Ws by synchronizing critical path’s delay Time

49. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 3: Minimize Delay Time 49 Minimize Ws Synthesize critical path’s delay time

50. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 Transistor Sizing 50  Design new topology adder  Synchronizing all path’s delay Time  Minimize Widths to save power dissipation 16 paths 24 paths 32 paths

51. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所Outline  Introduction  Convex Optimizing  Geometric Form  GP solver  Applications  Operating Amplifier  LNA  Adder  Future Challenge 51

52. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 Future Challenge  Thanks for RDC providing UMC 90nm tech.  Some papers about adders  Mathew, S.; Anders, M.; Krishnamurthy, R.K.; Borkar, S.; “A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core,” IEEE, JSSC JSSC Volume 38, Issue 5, pp. 689 – 695, May 2003.  Y. Shimazaki, R. Zlatanovici, B. Nikolic, “A Shared-Well Dual-Supply Voltage 64-bit ALU,” ISSCC Dig. Tech. Papers, pp.104-105, Feb., 2003.  S. Mathew, et al, “A 4GHz 300mW 64b Integer Execution Unit ALU with Dual Supply Voltages in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp.162-163, Feb., 2004.  Klaus von Arnim, Peter Seegebrecht, Rpland Thewes, Christian Pacha, “A Low-Leakage 2.5GHz Skewed CMOS 32b Adder for Nanometer CMOS Technologies,” ISSCC Dig.Tech.Papers, pp. 380-605, Feb., 2005.  Sean Kao, Radu Zlatanovici, Borivoje Nikolic, “A 240ps 64b Carry-Lookahead Adder in 90nm CMOS,” ISSCC Dig.Tech.Papers, pp. 1735-1744, Feb., 2006.  Wijeratne, S. B., Siddaiah, N., Mathew, S. K., Anders, M. A., Krishnamurthy, R. K., Anderson, J., Ernest, M., Nardin, M.,” A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit,” IEEE, JSSC Volume 42, Issue 1, pp.26 – 37, Jan. 2007.  Accuracy nonlinear Model ?  Chung-Ping Chen, Chris C. N. Chu, and D. F. Wong, "Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation," IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 18, No. 7, pp. 1014-1025, July 1999. 52

53. NTU GIEE Graduate Institute of Electronics Engineering National Taiwan University 國立台灣大學電子工程學研究所 53 Q & A