1. ECE 353 Introduction to Microprocessor Systems Discussion 8

2. Topics Memory Timing Analysis Q&A

3. ADuC7026 Memory System Timing Analysis Assume that we want two DS1230W-100 NVSRAMs in our system. Perform a timing analysis to determine if they will work. You only need to look at the read timing, and only the T ACC and T CO timings and verify that there is no data contention T OD. Microprocessor/Memory System

4. SRAM Timing Compatibility (from class notes:) In order to properly read and write the device, we need to ensure that the processor memory interface is compatible with the memory device. This is accomplished by analyzing the timing for all relevant parameters, and ensuring that the operation can be completed successfully. NVSRAM NVSRAM – Read Specs NVSRAM – Read Diagram

5. Assessing Timing Compatibility (from class notes:) Need to know whether CPU could operate with the t ACC for given device. We designate a CPU characteristic t AVDV, which is the delay from When the address becomes valid at the CPU Until the data must be driven to CPU This establishes an upper bound on t ACC t ACC < t AVDV Read cycle parameters Read cycle control Read Cycle Timing

6. System Timing Compatibility Need to account for all delays in a system to assess timing compatibility. Analyze the read timing with regard to: t ACC – address access time t CO – chip enable to valid data t OD – output hold/float time (contention) System Timing

7. Answer Parameters we need: CLK period – at 41.78 MHz, it will be 23.93 ns (round it to 24 ns for our calculations) Delays:  Latch: 15 ns  Decode: 8 ns Decode:  /MSx  /BxE  Pin A15 (A16 info)

8. tACC Analysis The address does not reach the NVSRAM until after it has propagated though the latch, so that shortens the available time for the SRAM to drive data. Since the SRAM must drive data BEFORE it is required at the processor, tACC < tAVDV – ½CLK - tLATCH tACC < 3CLK - TDATA_SETUP – ½CLK – tLATCH 100 <? 3*24 – 10 – 12 – 15 = 35 Margin: 35 – 100 = -65 ns margin – timing not met with default timings. We must add three CLKs of delay – could be in any place for this timing. tACC < 3CLK - TDATA_SETUP – ½CLK - tLATCH + tAW + (tAH + tRDTA + tW) x CLK Answer

9. tCO Analysis The chip enable is derived from some combination of the memory select (/MSx), the byte enables (/BHE, /BLE) and the address. Since our memory is byte writable (a reasonable assumption for a 16-bit memory), the last signal to arrive at the decoder will be the byte enables. The byte enables are asserted 1 clock before the rising edge of /RS. Since the SRAM must drive data BEFORE it is required at the processor, tCO < CLK - TDATA_SETUP – tDECODER 100 <? 24 – 10 – 8 = 6 Margin: 6 – 100 = -94 ns margin – timing not met with default timings. We must add four CLKs of delay – could be in any place except in the AE timing (tAW) for this timing. tCO < CLK - TDATA_SETUP – tDECODER + (tAH + tRDTA + tW) x CLK Answer

10. Summary We need at least four wait states (maximum between 3 and 4). We can add the four wait states any place except in the AE timing (tAW). (Before selecting where, it would be best to do the tOE timing to see if/where it needs additional time - tW.) Still need to look at tDO, data hold time, to make sure there is not an issue with data contention. Answer

11. Data Hold: Two Issues: 1) will NVSRAM hold the data valid long enough for the processor to read it properly? ADuC: tDATA_HOLD = 0 ?(no spec from ADI yet) NVSRAM: tOH (from address) = 5 ns min. Since the address is valid for one clock after /RS goes high (inactive), the hold time from address is 24 + 5 = 29. This is more than the 0 ns the processor requires. NVSRAM: tOD (from /CE or /OE) = 35 ns max. Since the minimum time is not given, if we assume a minimum of zero, the hold time from /CE or /OE is 0. This meets the 0 ns the processor requires. So, the NVSRAM will hold the data long enough for the processor to read it. Answer

12. Data Hold: 2) will the NVSRAM hold the data lines active too long? (i.e., will it still be driving the data lines when the processor starts to drive the next address onto them?) (assume the processor drives the next address one clock after /RS goes high.) ADuC: tADDR_AFTER_CLKH = 4 to 16 ns Taddr_after_rd = 28 to 40 ns The processor will start driving the address lines as soon as 28 ns after the /RS line goes high. NVSRAM: tOD (from /CE or /OE) = 35 ns max. Since the processor will start driving the address lines as soon as 28 ns after the /RS line goes high, we will have both devices trying to drive the lines – CONTENTION!! So, the NVSRAM will not be compatible due to bus contention issues. What to do? Find a different part with better characteristics (shorter tOD)? Use a transceiver? Answer

13. Questions?

14. Microprocessor/Memory System

15. Read Cycle Parameters

16. Read Cycle Controls

17. Read Cycle Timing Parameter MinTyp Max CLKUCLK T AE_H_AFTER_MS ½ CLK T AE (XMxPAR[14:12]+1) x CLK T HOLD_ADDR_AFTER_AE_L ½ CLK+(!XMxPAR[10] x CLK) T RD_L_AFTER_AE_L ½ CLK+((!XMxPAR[10] + !XMxPAR[9]) x CLK) T RD (XMxPAR[3:0]+1) x CLK T DATA_SETUP ? T DATA_HOLD ? T RELEASE_MS_AFTER_RD_H CLK

18. NVSRAM

19. NVSRAM – Read Specs

20. NVSRAM – Read Diagram

21. System Timing