1. Design of a RISC Processor Compatible with ARM Instruction Set AHMET GÜRHANLI LAB: BL405 SUPERVISER: 陳中平 教授

2. OUTLINE General Architecture Inputs and Outputs Components Instructions Simulation Results Conclusion

3. GENERAL ARCHITECTURE

5. ARM multi-cycle instruction pipeline operation

6. Fetch Stage

7. Decode Stage Decode/Execute Pipeline Registers

8. Execute Stage

9. INPUTS & OUTPUTS

11. COMPONENTS

12. Register Bank

13. Program Status Register

14. ALU

15. Multiplier

16. The Enhancements We Made Shortening the Branch Process From 3 cycles to 2 cycles Fastening the Abort Entry Procedure

17. The Original Instruction Pipeline

18. Our Design

19. Abort Entry In the original design in case of an abort the running instruction is processed until the end, and then re-processed after abort interrupt. This may cause unnecessary stalls up to 16 cycles In our design processor can stop instruction execution immediately in case of a memory abort.

20. INSTRUCTIONS

21. Branch

22. Data Processing

23. ADD R1,R0,#15

24. ARM Data Processing Instructions

25. Multiply Rd = Rs*Rm Multiply Rd = Rs*Rm+Rn Multiply Accumulate

26. Multiply MUL R4,R2,R1

27. Multiple Transfer LDMIA R0!,{R5-R8}

28. SIMULATION RESULTS before simulation: memory [ 200] = xxxxxxxx before simulation: memory [ 201] = xxxxxxxx before simulation: memory [ 202] = xxxxxxxx before simulation: memory [ 203] = xxxxxxxx before simulation: memory [ 204] = xxxxxxxx before simulation: memory [ 205] = xxxxxxxx before simulation: memory [ 206] = xxxxxxxx before simulation: memory [ 207] = xxxxxxxx before simulation: memory [ 208] = xxxxxxxx before simulation: memory [ 209] = xxxxxxxx before simulation: memory [ 210] = xxxxxxxx before simulation: memory [ 211] = xxxxxxxx before simulation: memory [ 212] = xxxxxxxx before simulation: memory [ 213] = xxxxxxxx before simulation: memory [ 214] = xxxxxxxx before simulation: memory [ 215] = xxxxxxxx before simulation: memory [ 216] = xxxxxxxx before simulation: memory [ 217] = xxxxxxxx before simulation: memory [ 218] = xxxxxxxx before simulation: memory [ 219] = xxxxxxxx

29. SIMULATION RESULTS after simulation: memory [ 200] = 00000111 after simulation: memory [ 201] = 00000000 after simulation: memory [ 202] = 00000000 after simulation: memory [ 203] = 00000000 after simulation: memory [ 204] = 00001111 after simulation: memory [ 205] = 00000000 after simulation: memory [ 206] = 00000000 after simulation: memory [ 207] = 00000000 after simulation: memory [ 208] = 11010000 after simulation: memory [ 209] = 00000000 after simulation: memory [ 210] = 00000000 after simulation: memory [ 211] = 00000000 after simulation: memory [ 212] = 01101001 after simulation: memory [ 213] = 00000000 after simulation: memory [ 214] = 00000000 after simulation: memory [ 215] = 00000000 after simulation: memory [ 216] = 00001111 after simulation: memory [ 217] = 00000000 after simulation: memory [ 218] = 00000000 after simulation: memory [ 219] = 00000000

30. CONCLUSIONS Architecture coding is almost finished. Simple synthesis of the design is successful. We will finish the design flow as soon as possible and make the design ready for tape- out.

31. THANK YOU