1. ARM Series Intro A Glimpse Of ARM Fundamental Principals And Trend ZuMin(033230)

2. Contents  Intro To ARM1-7  RISC In ARM  Basic Information  Memory Control Method in ARM1176JZ

3. Advanced RISC Machines  One of the most famous processor producer  Focus on producing RISC Processor  Emphasis on Performance—Price—Power  Proving Design & Technical Support  Led the evolution of RISE Processor and still Leading

4. Brief History About ARMS

5. Basic Information  Word 32bits in ARM system  Half-Word 16bits in ARM system  Byte 8bits in ARM system

6. THUMB  The microprocessor is compatible to 8/16bits devices because of the THUMB  ARM microprocessor has two working conditions ARM&THUMB  ARM 32bits Instructions  THUMB 16bits Instructions

7. Basic Registers  Unranked Register R0-R7  Banked Register R8-R14  PC R15  Current Program Status Register R16

8. ARM11 Microarchitecture  The ARM11, the first implementation of the new ARMv6 Instruction Set Architecture  Designed to deliver high-performance – efficiently.  The current implementation roadmap defines CPU products running at clock speeds forecast in excess of 1GHz.

9. ROAD MAP

10. Performance Characteristics

11. Memory System of ARM1176JZ  Cache Organization  MMU  TLB  DMA - Direct Memory Access  TCM - Tightly-coupled memory  Write Buffer

12. Cache Organization  Separate Instruction and Data Caches in a Harvard arrangement. So both store and load instruction on cost one cycle.  Four-way set associative cache of configurable size.  The caches are virtually indexed and physically tagged.  Both the Instruction Cache and the Data Cache can provide two words per cycle for all requesting sources.

13. Features of the cache system  The cache is a Harvard implementation (Separate Instruction and Data Caches ).  The other main operations performed by the cache is cache line Write-Back.  Cache replacement policies are Pseudo-Random or Round-Robin, Round-Robin uses a single counter for all sets, that selects the way used for replacement.  Cache lines can be either Write-Back or Write- Through,

14. TCM  Instruction TCM (ITCM)  Data TCM (DTCM)  The TCM is designed to provide low-latency memory that can be used by the processor without the unpredictability that is a feature of caches.  You can use such memory to hold critical routines. such as interrupt handling routines or real-time tasks where the indeterminacy of a cache is highly undesirable.

15. TCM Behavior  TCM forms a continuous area of memory that is always valid if the TCM is enabled. The TCM is used as part of the physical memory map of the system, and is not backed by a level of external memory with the same physical addresses. For this reason, the TCM behaves differently from the caches for regions of memory that are marked as being Write- Through Cachable. In such regions, no external writes occur in the event of a write to memory locations contained in the TCM.

16. MMU  Memory Management Unit  The processor MMU works with the cache memory system to control accesses to and from external memory.  The MMU also controls the translation of virtual addresses to physical addresses.

17. MMU In ARM11  The processor implements an ARMv6 MMU enhanced with features to provide address translation and access permission checks for all ports of the processor.  While controlling the translation of virtual addresses to physical addresses, MMU in ARM11 makes use of TLB(Translation Lookaside Buffers)

18. TLB  Translation Lookaside Buffers  A single set of two-level page tables stored in main memory controls the contents of the instruction and data side  MicroTLB -- The first level of caching for the page table information is a small MicroTLB of ten entries that is implemented on each of the instruction and data sides.  Main TLB -- the second layer in the TLB structure that catches the cache misses from the MicroTLBs. It provides a centralized source for translation entries. Misses from the instruction and data MicroTLBs are handled by a unified main

19. MicroTLB & MainTLB  MicroTLB -- The first level of caching for the page table information is a small MicroTLB of ten entries that is implemented on each of the instruction and data sides.  You can configure MicroTLB replacement to be round-robin or random. By default the round-robin replacement algorithm is used.  MainTLB -- the second layer in the TLB structure that catches the cache misses from the MicroTLBs. It provides a centralized source for translation entries. Misses from the instruction and data MicroTLBs are handled by a unified main

20. TLB & Cache & Mem

21. WRITE BUFFER  All memory writes take place using the Write buffer.  The Write buffer is a FIFO of outstanding writes to memory. It consists of a set of addresses and a set of data words, together with their size information.  If a sequence of data words is contained in the Write buffer, these are denoted as applying to the same address by the Write buffer storing the size of the store multiple. This reduces the number of address entries that must be stored in the Write buffer.

22. REFERENCES  《 ARM1176JZ_MANUAL 》  《 ARM 技术讲解 - ARM 高级工程师》  《 ARMTechSympKeynote2005ChinaJunTa n 》  《丰富应用推动结构体系技术创新 – ARM 》  《完整的系统开发解决方案 - ARM 》 -- 中国 技术行销经理 费浙平

23. The End