1. Silicon Graphics, Inc. Re-Configurable Application Specific Computing (RASC/FPGA) David Alexander Director of Engineering

2. slide no. 2 Scalable Global Shared Memory Structure 10s of Thousands of ports Globally addressable Flat & high bandwidth Flexible & configurable Multi-Paradigm Computing Terascale to Petascale Data Set...Bring Function to Data Globally addressable, universally accessible, high-bandwidth flat address space Addressing the transition from Terascale to Petascale computing Tightly coupling “best-of-breed” computation, I/O, and visualization paradigms to memory Scalable Global Shared Memory Structure Scalar General Purpose uP (Today) General Purpose Peer I/O (Today) Graphics (Today) APU/Configurable (FPGA/RASC) (Today-2006) Others…

3. slide no. 3 NUMAlink Fabric Global Shared Memory NL4 Ports (6.4GB/s x 2) FPGA, DSP, or ASIC TIO ASIC 6.4GB/s Scratch/FIFO Memory I/O Products: Athena…V2-6000 based, rack mount module…shipping today Abacus…Virtex 4 based, blade…in development pipeline Solution variants: Roll-your-own-code customers –User developed bitstreams using a variety of environments/tools –Subroutine or std library abstractions (MKL, VSIPL) Commercial apps cust…co-dev. specific use “appliance” with ISV/partners Addressing the Performance Challenge Integration into NUMAlink

4. slide no. 4 Development Environment Ease of Use 3 rd Party Development Tools –Celoxica, Impulse Acceleration, Mitrion, Starbridge/Viva, Nallatech –Support for user-developed HDL modules –Timing and routing…Synplicity & Xilinx ISE tools FPGA aware version of GDB –Capable of debugging the FPGA and System Software –Capable of multiple CPUs and multiple FPGAs Developing an FPGA-aware version of our performance tuning tool…Open Speedshop RASC Abstraction Layer –API developed…participation in OpenFPGA.org to drive standards –Developing a set of standard libraries (such as VSIPL, MKL)

5. slide no. 5 Nallatech & SGI Partnership Collaborative development of a compatible HW/SW infrastructure and development environment –Creation of seamless, extended product line –New multi-FPGA product which marries Nallatech’s DIME architecture with SGI’s NUMA architecture –Portability algorithm and applications implementations across both companies’ full FPGA product line –Streamline collaborative development of future products Enhanced algorithm/appliance implementation capabilities for appliance and program-specific opportunities Facilitate the definition and evolution of industry standards