1. 1 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 INTERPOSER-BASED INTEGRATION OF ADVANCED MEMORIES AND ASIC M. Waqas Chaudhary Advanced System Integration Group Fraunhofer IIS, Design Automation Division EAS

2. 2 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 AGENDA Motivation Memory-ASIC System ASIC Design cost modelling Trade-offs discussion Design Examples Conclusion

3. 3 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 Motivation Source: Yole Development How to find the best solution for high speed memory interface ? Source: m-tek.com

4. 4 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 2.5D Integration Interposer-based Integration (Technology summary) Passive die with TSVs, top and bottom metallization Carrier for active dies High interconnect density (e.g. 10µm width/spacing) Top-bottom or side-by-side configurations Integrated passives in interposer  Targets Dense integration of heterogeneous dies High performance systems (e.g. memory-processor interface)

5. 5 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 AGENDA Motivation Memory-ASIC System ASIC Design cost modelling Trade-offs discussion Design Examples Conclusion

6. 6 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 Tire pressure monitor Image sensor / processor integration Interposer für JEDEC WideIO/Processor Heterogeneous Integration Different examples

7. 7 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 Memories Overview Memory Per pin max data rate (Gb/s) Interface signals per channel 400-Gb/s data rate requirements ChannelsSignals Wide IO-21.067976582 HBM22022404 HMC15440160 LPDDR43.2458360

8. 8 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 AGENDA Motivation Memory-ASIC System ASIC Design cost modelling Trade-offs discussion Design Examples Conclusion

9. 9 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 DESIGN COST MODELLING

10. 10 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 DESIGN OPTIONS AND DEPENDENCIES

11. 11 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 AGENDA Motivation Memory-ASIC System ASIC Design cost modelling Trade-offs discussion Design Examples Conclusion

12. 12 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 TRADE-OFFS HMC compatible Serdes Phy cost Signal and power integrity Serdes power addition to the Interfaced CPU Package Interposer routing layers and widths for 2.5D systems Resistive loss in interposer for HBM IOs

13. 13 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 AGENDA Motivation Memory-ASIC System ASIC Design cost modelling Trade-offs discussion Design Examples Conclusion

14. 14 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 HMC BASED SYSTEM HMC (4-Link x16 lane) CPU 31mm 40 lanes

15. 15 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 HBM BASED SYSTEM HBM CPU 404 interconnects Min 1.21mm Interposer

16. 16 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 WIDE IO-2 BASED SYSTEM Wide IO-2 CPU 6 channels Min 1.04mm Interposer

17. 17 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 LPDDR4 2.5D SYSTEM LPDDR4 (Quad channel package x64) CPU 15mm LPDDR4 (Quad channel package x64) 15mm

18. 18 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 AGENDA Motivation Memory-ASIC System ASIC Design cost modelling Trade-offs discussion Design Examples Conclusion

19. 19 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 CONCLUSION

20. 20 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 150 / 200 / 300 mm wafer processing Design services and design tools Clean room facilities: 3500 m² Test / Analytic-Laboratories : 900 m² Fraunhofer Cluster 3D-Integration Members and Facts

21. 21 © Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015 Fraunhofer Cluster 3D-Integration Competencies and Services PROTOTYPING PILOT MANUFACTURING SMALL VOLUME PRODUCTION