1. PCI Team 3: Adam Meyer, Christopher Koch,
Michael Beck, and Patrick Gerber

2. What is it/What does it do
PCI
Peripheral Component Interconnect
High speed bus
Began in 1990
Intel
PCI 1.0 on June 22, 1992
PCI special interest group

3. Basic Structure 32-bit or 64-bit bus
5 functional groups of mandatory signal lines
4 functional groups of optional signal lines

4. Mandatory Signal Lines
System Pins – Clock and Reset Pins
Address and data pins – 32 lines that are time multiplexed for addresses and data. Also contains lines used to interpret and validate signal lines carrying addresses and data
Interface control pins – Control timing of transactions and provide coordination among initiators and targets

5. Mandatory Signal Lines
Arbitration pins – Non-shared lines (unlike most other PCI signal lines); each PCI master has its own pair of arbitration lines that connect it directly to the PCI bus arbiter
Error reporting pins – Report parity and errors

6. Optional Signal Lines
Interrupt pins – Provided for PCI devices that must generate requests for service; also non-shared lines as each PCI device has its own interrupt line(s)
Cache support pins – Necessary to support memory on PCI that can be cached; support snoopy cache protocols

7. Optional Signal Lines
64-bit bus extension pins – 32 lines that are time multiplexed for addresses and data combined with mandatory address/data lines; Some lines used to interpret and validate signal lines carrying addresses and data; two lines that enable two PCI devices to agree to 64-bit capability
JTAG/boundary scan pins – Support testing procedures defined by IEEE Standards

8. PCI Commands Activity occurs in form of transaction
Initiator
Target
Initiator determines next type of transaction
During the address phase of the transaction, the C/BE lines are used to signal the transaction type

9. PCI Commands Interrupt Acknowledge Special Cycle I/O Read I/O Write
Memory Read
Memory Read Line
Memory Read Multiple
Memory Write
Memory Write and Invalidate
Configuration Read
Configuration Write
Dual Address Cycle

10. PCI Commands Interrupt Acknowledge Special Cycle
Read command intended for the device that functions as an interrupt controller
Special Cycle
Used by initiator to broadcast a message to one or more targets
I/O Read Write Commands
Transfer data between the initiator and an I/O controller

11. PCI Commands Memory Read Write Commands Configuration Commands
Specify the transfer of a burst of data to and from memory
Configuration Commands
Allows initiator to read and update configuration parameters for the connected device
Dual Address Cycle
Indicates 64-bit addressing

12. Types of PCI
Conventional PCI
PCI-X (Extended)
PCI-e (Express)

13. Conventional PCI First Proposed by Intel in 1990 Originally
32 bit data path
33 Mhz bus frequency
Throughput of 133MB/sec
After Improvements
64 bit data path
Up to 533MHz bus frequency
Throughput of up to 532MB/sec

14. PCI-X Designed to supersede PCI
Backward compatible with PCI cards and slots
Focus is on server technologies
Throughput of up to 8.5GB/sec
Widely being replaced by PCI Express

15. PCI Express Different architectural structure
Uses a serial bus system as opposed to parallel
Five different types- PCIe x1, x4, x8, x16, x32
Replacing AGP video slots

16. PCI Data

17. PCI slots