1. MS_uC / fue1 / V01 6- 1 TIMx - Timer Programming Microcontroller TIMx - Timer Autumn term 2012

2. MS_uC / fue1 / V01 6- 2 TIMx - Timer Typical Timer Features zFour 16 bit Timers, support: yTwo Input Captures yTwo Output Compares yPWM Out yPWM Input yOne Pulse Mode zTwo Clocks: External clocks, Internal Events zPrescaler zDMA support ® Input Cap 2 Peripheral Bus TIMx_ETR Interrupt - Overflow, OCMP, ICAP 16 Bit Prescaler CK_INT Overflow Output Comp. 1 Output Comp. 2 Output Comp. Reg 2 Latch 2 IC1 IC2 OC1 OC2 Control Registers Trigger controller Input Cap 1 16-Bit Counter Register Output Comp. Reg 1 ITR0 ITR3 Latch 2 Edge Detect Circuit 2 Edge Detect Circuit 1

3. MS_uC / fue1 / V01 STM32F107xx Timer Modules RM0008 Reference manual zAdvanced-control timers: TIM1 & TIM8 y16-bit up, down, up/down auto-reloat counter y4 Indepent channels xInput capture, Output compare, PWM & OPM yComplementary outputs with programmable dead time zGeneral-purpose timers (TIM2 to TIM5) y16-bit up, down, up/down auto-reloat counter y4 Indepent channels zGeneral-purpose timers (TIM9 to TIM14) y16-bit up, down, up/down auto-reloat counter y2 Indepent channels zBasic Timers (TIM6 & TIM7) y16-bit up, down, up/down auto-reloat counter 6- 3 TIM - Timer

4. MS_uC / fue1 / V01 6- 4 TIM - Timer General-purpose timers main features (1/2) z16-bit up, down, up/down auto reload counter yProvide counter values for output compare and input capture z16-bit programmable pre scaler used to divide the counter clock frequency by any factor between 1 and 65’535 zUp to 4 independent channels for: yInput capture yOutput compare yPWM generation yOne pulse mode output zSynchronization circuit to control the timer with external signals and to interconnect several timers ®

5. MS_uC / fue1 / V01 General-purpose timers main features (2/2) zInterrupt/DMA generation on the following events yUpdate: counter overflow/underflow, counter initialization (by software or internal/external trigger) yTrigger event (counter start, stop, initialization or count by internal/external trigger) yInput capture yOutput compare zSupports incremental (quadrature) encode and hall-sensor circuitry for positioning purposes zTrigger input for external clock or cycle-by cycle current management 6- 5 TIM - Timer

6. MS_uC / fue1 / V01 6- 6 TIM - Timer TIMx modes of functionality zInput Capture Mode yTwo input pins, user programmable edge polarity yCapture counter values when input edge is detected yGenerate interrupt when enabled yCan measure input pulse width zOutput Compare Mode yTwo output compare pins, one for each compare register yCompare Register is compared with counter value yGenerate output signal/waveform on pin when a match occurred yUser programmable output signal level zOther Timer Modes yBased on the Input Capture and Output Compare logic xOne Pulse Mode xPWM Output Mode xPWM Input Mode ®

7. MS_uC / fue1 / V01 6- 7 TIM - Timer TIMx PWM output mode zAutomatic generation of a Pulse Width Modulated signal yFrequency determined by TIMx_ARR register yDuty cycle corresponds to TIMx_CCRx register zConfiguration for the PWM output mode zOCxM bits in the TIMx_CCMRx register selects the PWM output mode for OCx zOCxPE bit in the TIM_CCMRx register enables the corresponding preload register zARPE bit in the TIMCR1 register enables auto-reload preload register zCCxP bit in the TIM_CCER register defines the polarity of the OCx output zCCxE bit in the TIM_CCER register enable the OCx output zThe duty cycle is stored in TIMx_CCR1 register zThe full period is stored in TIMx_ARR register TIMx_CCR1 = 0x2ED0 TIMx_ARR = 0x34E2 CC1P = 0 OLVL2 0000 0001 0002 34E2 2ED02ED1…0000 Counter OC1 CC1P = 0 Compare 1Compare 2 34E2 Compare 2 34E22ED0 ®

8. MS_uC / fue1 / V01 6- 8 TIM - Timer TIMx PWM input mode zExternal pulse and period measurement of an external wave yProgrammable first edge detection yInterrupt Generation zConfiguration for the PWM input mode zCC1S bits of TIMx_CCMR1 register select the input for TIMx_CCR1 (TI1) zCC1P bit of TIMx_CCER register selects the active polarity of TI1 (rising edge) zCC2S bits of TIMx_CCMR2 register select the input for TIMx_CCR2 (TI1) zCC2P bit of TIMx_CCER register selects the active polarity of TI1 (falling edge) zTS bits of TIMx_SMCR register select TI1FP1 as trigger for the slave controller zSMS bits of TIMx_SMCR register configure the slave controller in reset mode zCC1E and CCE2 bits of the TIMx_CCER register enable the captures Period = TIMx_CCR2 Pulse Length = TIMx_CCR1 0000 0001 0002 34E2 2ED02ED1…0000 Counter TI1 IC2 captureIC1 capture 34E2 IC1 capture TIMx_CCR1 = 0x2ED0 TIMx_CCR2 = 0x34E2 CC1S = 0b01 CC2S = 0b10 CC1P = 0 CC2P = 1

9. MS_uC / fue1 / V01 TIMx one pulse mode 6- 9 TIMx - Timer zGeneration of a pulse synchronized with an external event zParticular case of the previous modes zStarting the controller can be controlled by the slave mode controller zGeneration the waveform can be done in output compare mode TIMx_CCR1 = 0x2ED0 TIMx_ARR = 0x2ED3 CC1P = 0 CC1P = 1 FFFC 0001 0002 … 2ED02ED1 2ED2 2ED30000 Counter TI2 OC1 CC1P = 1 Compare 1 0000 2ED0 zConfiguration for the one pulse mode zOPM bit of TIMx_CR1 register selects one pulse mode zIC2S bits of TIMx_CCMR1 register maps TI2FP2 on TI2 zCC2P bits of TIMx_SMCR register select the rising edge detection for TI2FP2 zTS bits of TIMx_SMCR register configure TI2FP2 as trigger for the slave mode controller zSMS bits of TIMx_SMCR register enable TI2FP2 signal to start the counter zTIMx_CCR1 register defines the passive period zTIMx_ARR – TIMx_CCR1 defines the active period zCC1P bit of TIMxCCMR1 register fix the polarity of the active signal ®

10. MS_uC / fue1 / V01 6- 10 TIM - Timer General purpose timer block diagram

11. MS_uC / fue1 / V01 6- 11 TIM - Timer Presaler zThe prescaler can divide the counter clock frequency by any factor between 1 & 65536 zItis based on a 16-bit counter controlled through a 16-bit register (TIMx_PSC register)

12. MS_uC / fue1 / V01 6- 12 TIM - Timer Timer Register Map (1/3) RM0008 Reference manual (page 407)

13. MS_uC / fue1 / V01 6- 13 TIM - Timer Timer Register Map (2/3)

14. MS_uC / fue1 / V01 Timer Register Map (3/3) 6- 14 TIM - Timer

15. MS_uC / fue1 / V01 6- 15 TIM - Timer ARM Peripheral Bus 2 access (APB2) RM0008 Reference manual (page 51)

16. MS_uC / fue1 / V01 6- 16 TIM - Timer ARM Peripheral Bus 1 access (APB0)