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Free Running Counter & Real Time Control

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Presentation on theme: "Free Running Counter & Real Time Control"— Presentation transcript:

1 Free Running Counter & Real Time Control

2 Because there is no accounting for time spent in real time….
The programming for Loading of a timer, start, stop are not appropriate for REAL TIME CONTROL. Because there is no accounting for time spent in real time…. In real time we have to use a “FREE RUNNING COUNTER”

3 Free running counter, which does not have
A Counter stop programming feature & counter value loading capability Once it starts on power up of the MC, it keeps running endlessly even after overflow. This free running counter keeps record of the actual time (Real Time) Watch is the example for FRC A watch show a real time & can be used to manage the events in the real time. Similarly FRC can manage the events in real time space

4 Using an output compare register along with a timer running as a free running counter:
Clock is used to raise an alarm at a prefixed instance. The real time show by the clock continuously compares with a preset value. As the real time shown by the clock equals the preset time value, the alarm raises. Similarly, one of the uses of a FRC is that it can be used to raise an interrupt when the timer count value equals a preset value in an out-compare register associated with the timer.

5 Using an input capture register:
The time at which the event occurred is to be noted by capturing the exact instant (or) The time interval between two events is to be noted by capturing these instances For this, an input capture register is used along with a timer running as a free-running counter

6 Interrupt Interval and Density constraints:
Interrupt latency can be defined as the interval b/w the occurrence of the interrupt event and the start of the interrupt service for that event. Interrupt Service Latency Latency when no other higher priority than the Present one is pending the service Interrupt latency longest period, TL is depending on follg., factors Longest Instruction Execution Period, Tinst Period Tenwait, during which the interrupt remains disabled and waits for enabling the interrupt

7 Latency when other higher priority interrupts than the present one is pending the service
Worst case latency period will be the sum of the Tinst+Tinitial+Tend+TH Tinitial is period of initial actions like disabling the interrupt and saving the CPU registers onto the stack Tend is Time taken in reassigning priorities, re-enabling and retrieving the stack TH is the time of initializing, execution, & ending of each of the higher than the present interrupt that required the service

8 Interrupt Service Intervals:
Interrupt service period of an ith interrupt task is Ti=Tinitial+Texecution+Tend Assume that the interrupt interval b/w the successive ith interrupt is T’intv then (Ti/T’intv) is the fraction of time spent in an interrupt service

9 Interrupt Density: Assume that the interrupt interval b/w the ith interrupt events & Assume that there are ‘n’ interrupts. (Ti/T’intv) is the fraction of time spent in an interrupt service Interrupt Density = ∑ (Ti/T’intv)


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