1. 1. Introduction 2. Methods for I/O Operations 3. Buses 4. Liquid Crystal Displays 5. Other Types of Displays 6. Graphics Adapters 7. Optical Discs 10/01/20151Input/Output Systems and Peripheral Devices (02-1)

2. Programmed I/O Interrupt-Driven I/O Direct Memory Access (DMA) I/O Processors 10/01/20152Input/Output Systems and Peripheral Devices (02-1)

3. Principle of Programmed I/O I/O Device Addressing I/O Instructions Disadvantages of Programmed I/O 10/01/20153Input/Output Systems and Peripheral Devices (02-1)

4. Data are transferred between the CPU and I/O module under direct control of the CPU Each transfer operation requires the execution of an instruction sequence by the CPU The transfer is carried out between a CPU register and a register of the I/O device The I/O device does not have direct access to main memory 10/01/20154Input/Output Systems and Peripheral Devices (02-1)

5. Execution of an I/O operation: The CPU sends a command to the I/O module The I/O module performs the requested action and sets the appropriate bits in the status register The CPU must check periodically the status of the I/O module to detect that the operation is complete 10/01/20155Input/Output Systems and Peripheral Devices (02-1)

6. Principle of Programmed I/O I/O Device Addressing I/O Instructions Disadvantages of Programmed I/O 10/01/20156Input/Output Systems and Peripheral Devices (02-1)

7. The CPU, memory, and I/O devices usually communicate via the system bus An I/O device is connected to the bus via an I/O port  addressable register When the CPU, main memory, and I/O system share a common bus, two addressing techniques are possible: Memory-mapped addressing Isolated addressing 10/01/20157Input/Output Systems and Peripheral Devices (02-1)

8. Memory-mapped addressing There is a single address space for memory locations and I/O devices The CPU treats the status and data registers of I/O modules as memory locations The same instructions are used to access both memory and I/O devices No special I/O instructions are needed  memory load and store instructions 10/01/20158Input/Output Systems and Peripheral Devices (02-1)

9. The RD and WR control lines are used to initiate either a memory access cycle or an I/O transfer 10/01/2015 Input/Output Systems and Peripheral Devices (02-1) 9

10. Isolated Addressing The I/O address space is isolated from that for memory The bus must contain: Read and write lines for the memory Command lines for input and output A memory-referencing instruction asserts the MRD or MWR control line The CPU must execute separate I/O instructions to assert the IORD and IOWR lines 10/01/201510Input/Output Systems and Peripheral Devices (02-1)

11. 10/01/201511Input/Output Systems and Peripheral Devices (02-1)

12. Principle of Programmed I/O I/O Device Addressing I/O Instructions Disadvantages of Programmed I/O 10/01/201512Input/Output Systems and Peripheral Devices (02-1)

13. Programmed I/O can be implemented by at least two I/O instructions IN, OUT (Intel) To prevent the loss of information or an indefinite execution time, the CPU must test the status of the I/O device To execute an I/O instruction, the CPU sends: An address: the I/O module and the external device An I/O command 10/01/201513Input/Output Systems and Peripheral Devices (02-1)

14. Types of I/O commands Control: used to activate a peripheral and to specify the operation to be executed Test: used to test status conditions associated with an I/O module and its peripherals Read: used to obtain a byte or word from the peripheral Write: used to send a byte or word to the peripheral 10/01/201514Input/Output Systems and Peripheral Devices (02-1)

15. Reading a block of data from a peripheral device into memory For each word that is read in, the CPU must remain in a cycle to test the status 10/01/201515Input/Output Systems and Peripheral Devices (02-1)

16. The programmer’s interface for a terminal keyboard Exemplifying the programmed I/O for memory- mapped addressing and isolated addressing 10/01/2015 Input/Output Systems and Peripheral Devices (02-1) 16

17. Memory-mapped addressing 512 memory locations (0-1FFh) 512 I/O addresses (200h-3FFh) Reading a byte from the keyboard LDAC, 1 ST301h, AC; start keyboard read WAIT:LDAC, 301h; read status byte ANDAC, 80h; isolate bit 7 BZWAIT; wait for the byte LDAC, 300h; read data byte 10/01/201517Input/Output Systems and Peripheral Devices (02-1)

18. Isolated addressing The I/O ports have the same addresses as in the previous example Reading a byte from the keyboard LDAC, 1 OUT301h, AC; start keyboard read WAIT:INAC, 301h; read status byte ANDAC, 80h; isolate bit 7 BZWAIT; wait for the byte INAC, 300h; read data byte 10/01/201518Input/Output Systems and Peripheral Devices (02-1)

19. Principle of Programmed I/O I/O Device Addressing I/O Instructions Disadvantages of Programmed I/O 10/01/201519Input/Output Systems and Peripheral Devices (02-1)

20. Performance of the system is significantly reduced, because: The CPU has to wait until the peripheral becomes available, and then to execute the transfer by a program sequence The transfer rate is limited by the speed with which the CPU can test and serve the I/O devices 10/01/201520Input/Output Systems and Peripheral Devices (02-1)

21. Programmed I/O: the CPU executes a sequence of instructions for each transfer Addressing techniques Memory-mapped addressing: the registers of I/O modules are treated as memory locations Isolated addressing: the registers of I/O modules have addresses in an address space separated from that of the memory Programmed I/O has major disadvantages 10/01/201521Input/Output Systems and Peripheral Devices (02-1)

22. Principle of programmed I/O Execution of an I/O operation I/O port Memory-mapped addressing Isolated addressing Disadvantages of programmed I/O 10/01/201522Input/Output Systems and Peripheral Devices (02-1)

23. 1.How is an I/O operation executed with programmed I/O? 2.What are the differences between memory-mapped addressing and isolated addressing? 3.What are the disadvantages of programmed I/O? 10/01/201523Input/Output Systems and Peripheral Devices (02-1)