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Boolean Algebra (Continued) ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

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Presentation on theme: "Boolean Algebra (Continued) ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning."— Presentation transcript:

1 Boolean Algebra (Continued) ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning

2 311_032 Exclusive-OR (XOR)

3 XOR Theorems 311_033

4 Equivalence 311_034

5 Equivalence (XNOR) 311_035

6 6 Project 1  Combinational Circuit Analysis Determine input/output relationship of function Boolean Equation Truth Table Implement logic circuit with FPGA Schematic capture design tools Test circuit to verify operation Project Report  Teams of 2 persons

7 311_037 Xilinx ISE Design Suite  Enter description of logic circuit Schematic editor VHDL  Use a logic synthesizer to generate a netlist  Use implementation tools to map logic gates and interconnections into the FPGA  Generate a bitstream programming file  Configure device Download the bitstream to the FPGA chip

8 or Schematic 8311_03

9 9

10 10 New Project  File → New Project Project Name Demo1 Project Location C:\xxx\xxx Top-Level Module Type Schematic Device Family Spartan3E Device XC3S100E Package TQ144 (BASYS) CP132 (BASYS 2) Speed Grade -5

11 311_0311 New Source  Project → New Source Schematic Demo1  Schematic Editor Symbols Category list Symbol list Drawing area Tools Add wire Add I/O marker

12 add wire add I/O marker 12311_03

13 13 Demo1 Schematic  Categories Logic  Symbols and2 and3 inv or2  Add wires Point to point Stubs  I/O Markers Input marker Output marker Rename Port

14 Switches LEDs FPGA 14311_03

15 15 FPGA Pins

16 311_0316 Constrain the Design  User Constraints → I/O Pin Planning – Pre-Synthesis Implementation Constraints File Demo1.ucf PlanAhead I/O Ports  Site I/O NameLocationBASYSBASYS 2 XSW2P29 K3 YSW1P36 L3 ZSW0P38 P11 XYLD1P14 M11 FLD0P15 M5

17

18 311_0318 Synthesize & Implement  Synthesize Design  Implement Design  Generate Programming File

19 311_0319 BASYS Configuration Set to ROM

20 311_0320 Configure Device  Configure Device (Adept) Initialize Chain XCF02S (PROM) demo1.bit Program Cycle Power (Reset)

21 311_0321

22 311_0322 Test the Design XYZ F 0 1 XY

23 311_0323 Project Report  Cover Sheet Project Name/Number Authors Professor’s Initials  Objectives  Discussion Boolean Equation Truth Table Circuit Schematic  Conclusion Test Results

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