1. Mateusz Baszczyk, Piotr Dorosz, Wojciech Kucewicz, AGH-UST Krakow Claudio Gotti, Gianluigi Pessina, INFN-Milano Bicocca Angelo Cotta Ramusino, INFN-Ferrara CLARO 8ch ASIC: configuration register with Triple Modular Redundancy protection 1

2. Topic introduction TMR protected configuration register compatible with the SPI port of the GBT-SCA device preliminary pad assignment proposed mixed signal design flow HDL synthesis with RTL Compiler preliminary floorplan for analog and digital parts preliminary P&R of configuration register extra slides: detailed information 2

3. GBT-SCA, a general-purpose integrated circuit for the monitoring and control of the electronics in HEP experiments The Slow Control Adapter (SCA) chip is designed to work in parallel with to the GBT optical link bidirectional transceiver system of which it extends the functionality. introduction 3

4. (*) GBT-SCA: The Slow Control Adapter for the GBT System Alessandro Gabrielli, Kostas Kloukinas, Paulo Moreira, Alessandro Marchioro, Sandro Bonacini, Filipe Sousa The current CLARO prototype will be upgraded with an SPI-compliant configuration register, so that configuration and monitoring of the upgraded RICH front end electronics will be handled by the GBT-SCA ASIC (*) The 128bit ( it was 64 at the time of the review) configuration/status register being proposed here is protected by TMR (Triple Modular Redundancy). An “nSEU_detected” CLARO output pin (open drain) activates when bit flip(s) occur in any TMR cell. A pulse on the “SEU correct” CLARO input pin repairs the bit flip and this clears, in turn, the “SEU_detected” flag. The occurrences of “SEU_detected” onsets could be detected, counted and cleared through the GBT-SCA general purpose parallel I/O (PIA) ports. The current version of CLARO configuration/status register presented here also foresees a self correction circuit for the SEU events. This feature is accompanied by an internal counter for “SEU_detected” events, whose value is read back, along with the TMR-protected configuration bits, on every 128-bit SPI transaction scheduled by the GBT-SCA. 4

5. TMR protected configuration register compatible with the SPI port of the GBT-SCA device CLARO configuration block design hierarchy I/O Shift register connected to the SPI interface SPI inSPI out block diagram of the CLARO configuration block from I/O shift register (96+8)bit storage register A to voter/SEU detect from voter (96+8)bit storage register B to voter/SEU detect from voter (96+8)bit storage register C to voter/SEU detect from voter (96+8)bit majority voter A ABC BC (96+8)bit SEU detect ABC cfg bits to CLARO core to registers MUX 16 bit SEU counter 128 bit parallel input port for data to shift out SEU self correction pulse generator to storage reg. from self corr. pulse generator from self corr. pulse generator from self corr. pulse generator 5

6. preliminary pad assignment agndagnd agndagnd agndagnd agndagnd agndagnd agndagnd TOP VIEW in1in1 in2in2 in3in3 in4in4 in5in5 in6in6 TEST analog voltage level in0 in7 Input amplifiers Threshold DACs Output comparators Configuration register with SPI interface and TMR protection tstp1 (amp 0 output) amp_bias_current tstp2 (dac0 output) SPI_CLK MOSI SEU_generation_enable MISO SEU_CORRECT_clk nSEL nSEU_detected_OC_out TEST_PULSE_IN out0out7 dgnddgnd dvdddvdd dgnddgnd dgnddgnd dvdddvdd dgnddgnd out1out1 out2out2 out3out3 out4out4 out5out5 out6out6 avdd CHAIN_ENABLE_IN dvdd thresh_current avdd comp_bias_current after a few iterations with C. Gotti dgnd 6

7. HDL Description RTL Compiler Report Timing, Hierarchy Config Files, Attributes, Constraints Config Files, Attributes, Constraints Synthesis RQMT Met? RQMT Met? EncounterEncounter Attributes, Constraints Attributes, Constraints RQMT Met? RQMT Met? Floorplanning Digital Parts Non-timing Placement Non-timing Placement Pre CTS Flow Post CTS Flow Post Route Flow Encounter/ Virtuoso Chip Assembly Mixed Signal Routing VirtuosoVirtuoso Simulation RQMT Met? RQMT Met? Design Check RTL Simulation SIGNOFF INIT EncounterEncounter Floorplanning Analog and Digital Power Routing Partitioning VirtuosoVirtuoso Floorplanning Analog Parts Simulation Design Flow 7

8. RTL Compiler Part of Configuration file, which prevents from deleting TMR: set_attribute merge_combinational_hier_instance false synthesize -to_generic -csa_effort medium -effort medium # Perform Generic Optimisation synthesize -to_mapped -effort medium # Perform technology mapping and optimisation Synthesis Triple Modular Redundancy Trzeba odpowiednio skonfigurować program, aby nie wyrzucił redundancji 8

9. Encounter Digital Part Analog Parts (define as Black Box with In/Out Pins) Floorplanning Analog and Digital Partitioning In/Out Pad Ring 9

10. Encounter TMR modules were defined as Fences then Standard Cells for each module were placed separately, which should prevent from double errors. Floorplanning Digital Part Non-timing Placement Non-timing Placement Physical View Amoeba View Voter and Registers A Voter and Registers B Voter and Registers C 10

11. Encounter Because technology contains four metals – for routing ‚wroute’ command was used. Physical View Amoeba View Voter and Registers A Voter and Registers B Voter and Registers C Post CTS Flow Post Route Flow Deafult optimization parameters were change (,optDesign’ command), because Encounter was deleting TMR modules. In Design Optimization some Standard Cells were moved (TMR separation was disturbed), in another case routing ends with DRC violations and timing mismatches (i.e.) 11

12. Encounter Post CTS Flow Post Route Flow Buffers Clock Buffers Hierarchical View Voters A, B, C Registers A,B, C SEU detector 12

13. Encounter Post Route Flow Clock coinstraints Design meets timing constraints Report WNS parameter is positive 13

14. Detailed Information 14

15. Encounter Post CTS Flow Hierarchical View Deleted Voters B and C Optimization with default parameters deletes TMR modules. 15

16. Encounter Post CTS Flow Every hierarchical module was define as Fence. Optimization with presented parameters doesen’t delete TMR modules, and enable wrouter routes nets without violations, but it disturbs TMR modules separation. setOptMode -simplifyNetlist false -deleteInst false -restruct false -downsizeInst false optDesign -postCTS Screens present hierarchical modules placement – they are selected in red SEU Detector 16

17. Encounter Post CTS Flow Voter C 17

18. Encounter Post CTS Flow Registers C 18

19. Encounter Post CTS Flow Voter B 19

20. Encounter Post CTS Flow Registers B 20

21. Encounter Post CTS Flow Voter A 21

22. Encounter Post CTS Flow Registers A 22

23. Encounter Post CTS Flow TMR output 23