1. 1 SEA_uniovi_CC1_00 Lección 4 Teoría básica de los convertidores CC/CC (I) (convertidores con un único transistor) Diseño de Sistemas Electrónicos de Potencia 4º Curso. Grado en Ingeniería en Tecnologías y Servicios de Telecomunicación Universidad de Oviedo

2. 2 Introducing switching regulators Basis of their analysis in steady state Detailed study of the basic DC/DC converters in continuous conduction mode Buck, Boost and Buck-Boost converters Common and different properties Introduction to the synchronous rectification Four-order converters Outline (I) SEA_uniovi_CC1_01

3. 3 Study of the basic DC/DC converters in discontinuous conduction mode DC/DC converters with galvanic isolation How and where to place a transformer in a DC/DC converter The Forward and Flyback converters Outline (II) SEA_uniovi_CC1_02

4. 4 Linear DC/DC conversion (analog circuitry) First idea  = (v O i O )/(v g i g ) i O  i g  v O /v g Actual implementation - V ref AvAv Feedback loop vEvE RLRL vgvg vOvO Q iOiO igig  Only a few components  Robust  No EMI generation  Only lower output voltage  Efficiency depends on input/output voltages  Low efficiency  Bulky - V ref AvAv Feedback loop vEvE RLRL vgvg vOvO RVRV iOiO igig SEA_uniovi_CC1_03

5. 5 Linear versus switching DC/DC conversion Linear - V ref AvAv Feedback loop vEvE RLRL vgvg vOvO Q iOiO igig Switching (provisional) - V ref AvAv Feedback loop vEvE RLRL vgvg vOvO S iOiO igig PWM vOvO vgvg t Features:  100% efficiency  Undesirable output voltage waveform v O_avg SEA_uniovi_CC1_04

6. 6 Introducing the switching DC/DC conversion (I) Basic switching DC/DC converter (provisional) - V ref AvAv Feedback loop vEvE RLRL vgvg vOvO S iOiO igig PWM vOvO vgvg t v O_avg The AC component must be removed!! - V ref AvAv Feedback loop vEvE RLRL vgvg vOvO S iOiO igig PWM Filter VOVO VgVg t RLRL vgvg vOvO S iOiO igig C filter It doesn’t work!!! SEA_uniovi_CC1_05

7. 7 Introducing the switching DC/DC conversion (II) Basic switching DC/DC converter vDvD VgVg t VOVO - V ref AvAv Feedback loop vEvE RLRL vgvg vOvO S iOiO igig PWM Filter LC filter Infinite voltage across L when S 1 is opened It doesn’t work either!!! RLRL vgvg vOvO S iOiO igig LC filter iLiL C L RLRL vgvg vOvO S iOiO igig iLiL C L iDiD D vDvD + - + - Including a diode SEA_uniovi_CC1_06

8. 8 Introducing the switching DC/DC conversion (III) Buck converter RLRL vgvg vOvO S iOiO igig LC filter iLiL C L iDiD D vDvD + - + - RLRL vgvg vOvO S iOiO igig iLiL C L iDiD D vDvD + - + - iSiS Starting the analysis of the Buck converter in steady state:  L & C designed for negligible output voltage ripple (we are designing a DC/ DC converter)  i L never reaches zero (Continuous Conduction Mode, CCM)  The study of the Discontinuous Conduction Mode (DCM) will done later t iLiL CCM t iLiL DCM SEA_uniovi_CC1_07

9. 9 First analysis of the Buck converter in CCM - RLRL vgvg vOvO S iOiO igig iLiL C L iDiD D vDvD + + - iSiS (In steady-state) - RLRL vOvO iOiO iLiL C L vDvD + + LC filter vDvD vgvg t v D_avg The AC component is removed by the filter Analysis based on the specific topology of the Buck converter = v O v O = v D_avg = d·v g T dT t vDvD vOvO vgvg d: “duty cycle”  This procedure is only valid for converter with explicit LC filter SEA_uniovi_CC1_08

10. 10 Introducing another analysis method (I)  Obviously, there is not an explicit LC filter  Therefore, we must use another method R VgVg VOVO + - igig iSiS iDiD L1L1 C2C2 S D i L2 L2L2 C1C1 + - Could we use the aforementioned analysis in the case of this converter (SEPIC)? SEA_uniovi_CC1_09

11. 11 Introducing another analysis method (II) Powerful tools to analyze DC/DC converters in steady-state Step 1- To obtain the main waveforms (with no quantity values) using Faraday’s law and Kirchhoff’s current and voltage laws Step 2- To take into account the average value of the voltage across inductors and of the current through capacitors in steady-state Step 2 (bis)- To use the volt·second balance Step 3- To apply Kirchhoff’s current and voltage laws in average values Step 4- Input-output power balance SEA_uniovi_CC1_10

12. 12 Introducing another analysis method (III) Any electrical circuit that operates in steady-state satisfies:  The average voltage across an inductor is zero. Else, the net current through the inductor always increases and, therefore, steady-state is not achieved  The average current through a capacitor is zero. Else, the net voltage across the capacitor always increases and, therefore, steady-state is not achieved + - v L_avg = 0 i C_avg = 0 VgVg Circuit in steady-state L C SEA_uniovi_CC1_11

13. 13 Introducing another analysis method (IV) Particular case of many DC/DC converters in steady-state:  Voltage across the inductors are rectangular waveforms  Current through the capacitors are triangular waveforms + - vLvL iCiC VgVg Circuit in steady-state L C v L_avg = 0 i C_avg = 0 T dT vLvL t - + v1v1 -v 2 t iCiC - + Volt·second balance: V 1 dT – V 2 (1-d)T = 0 Same areas SEA_uniovi_CC1_12

14. 14 VgVg i L1 iSiS L1L1 S L2L2 C1C1 + - i C1 v L1 + - v L2 + - v C1 Example Introducing another analysis method (V) Any electrical circuit of small dimensions (compared with the wavelength associated to the frequency variations) satisfies:  Kirchhoff’s current law (KCL) is not only satisfied for instantaneous current values, but also for average current values  Kirchhoff’s voltage law (KVL) is not only satisfied for instantaneous voltage values, but also for average voltage values  KVL applied to Loop1 yields: v g - v L1 - v C1 - v L2 = 0 v g - v L1_avg - v C1_avg - v L2_avg = 0 Therefore: v C1_avg = v g  KCL applied to Node1 yields: i L1 - i C1 - i S = 0 i L1_avg - i C1_avg - i S_avg = 0 Therefore: i S_avg = i L1_avg Loop1 Node1 SEA_uniovi_CC1_13

15. 15 Introducing another analysis method (VI) A switching converter is (ideally) a lossless system RLRL vgvg vOvO iOiO igig + - Switching-mode DC/DC converter  Input power: P g = v g i g_avg  Output power: P O = v O i O = v O 2 /R L  Power balance: P g = P O DC Transformer vgvg iOiO i g_avg RLRL vOvO + - 1:N  A switching-mode DC/DC converter as an ideal DC transformer being N = v O /v g Important concept!! i g_avg = i O v O /v g = N·i O Therefore: v g i g_avg = v O 2 /R L SEA_uniovi_CC1_14

16. 16 Steady-state analysis of the Buck converter in CCM (I) Step 1: Main waveforms. Remember that the output voltage remains constant during a switching cycle if the converter has been properly designed RLRL vgvg vOvO S iOiO igig iLiL C L iDiD D vDvD + - + - iSiS vSvS + - iOiO iLiL RLRL vgvg vOvO C L + - During dT S on, D off iOiO iLiL RLRL vOvO C L + - During (1-d)T S off, D on t t t t iSiS iDiD iLiL Driving signal dT T SEA_uniovi_CC1_15

17. 17 Step 1: Main waveforms (cont’) RLRL vgvg vOvO S iOiO iLiL C L D vDvD + - + - vSvS + - Steady-state analysis of the Buck converter in CCM (II) vLvL + - dT v g -v O S off, D on, (1-d)T iOiO iLiL RLRL vOvO C L + - vLvL + - S on, D off, dT iOiO iLiL RLRL vgvg vOvO C L + - vLvL + - T - v O Driving signal t t t vLvL iLiL i L_avg iLiL  From Faraday’s law:  i L = v O (1-d)T/L SEA_uniovi_CC1_16

18. 18 + - Step 2 and 2 (bis): Average inductor voltage and capacitor current Steady-state analysis of the Buck converter in CCM (III) dT v g -v O T - v O Driving signal t t t vLvL iLiL i L_avg  KCL applied to Node1 yields: i L - i C - i O = 0 i L_avg - i C_avg - i O = 0 Therefore: i L_avg = i O = v O /R L  Volt·second balance over L: (v g - v O )dT - v O (1-d)T = 0 Therefore: v O = d·v g (always v O < v g ) RLRL vOvO iOiO iLiL C L + - vLvL + - iCiC Node1 vgvg S igig iDiD D iSiS  Average value of i C : i C_avg = 0 Step 3: Average KCL and KVL: Step 4: Power balance: i g_avg = i S_avg = i O v O /v g = d·i O SEA_uniovi_CC1_17

19. 19 Summary Steady-state analysis of the Buck converter in CCM (IV) RLRL vgvg vOvO S iOiO igig iLiL C L iDiD D vDvD + - + - iSiS vSvS + - iOiO t t t iSiS iDiD iLiL dT T t iLiL t Driving signal vDvD vgvg i L_avg = i O = v o /R L v O = d·v g (always v O < v g ) i g_avg = i S_avg = d·i O i D_avg = i L_avg - i S_avg = (1-d)·i O  i L = v O (1-d)T/L i L_peak = i L_avg +  i L /2 = i O + v O (1-d)T/(2L) v Smax = v Dmax = v g i S_peak = i D_peak = i L_peak SEA_uniovi_CC1_18

20. 20 Steady-state analysis of the Boost converter in CCM (I) t t t t iSiS iDiD iLiL Driving signal dT T Can we obtain v O > v g ?  Boost converter S on, D off, during dT iLiL vgvg L vLvL + - Step 1: Main waveforms + - C vgvg iLiL iSiS L S iDiD D RLRL vOvO iOiO + - vLvL +- igig S off, D on, during (1-d)T iOiO iLiL RLRL vOvO C L + - vLvL + - iLiL  From Faraday’s law:  i L = v g dT/L SEA_uniovi_CC1_19

21. 21 Steady-state analysis of the Boost converter in CCM (II) Step 2 and 2 (bis): Average values  KCL applied to Node1 yields: i D - i C - i O = 0 i D_avg - i C_avg - i O = 0 Therefore: i D_avg = i L_avg (1-d) = i O = v O /R L  Volt·second balance over L: v g dT - (v O - v g )(1-d)T = 0 Therefore: v O = v g /(1-d) (always v O > v g )  Average value of i C : i C_avg = 0 Step 3: Average KCL and KVL: Step 4: Power balance: i g_avg = i L_avg = i O v O /v g = i O /(1-d) + - C vgvg iLiL iSiS L S iDiD D RLRL vOvO iOiO + - vLvL +- igig iCiC Node1 dT vgvg T Driving signal t t t vLvL iDiD i D_avg iLiL -(v O -v g ) SEA_uniovi_CC1_20

22. 22 Steady-state analysis of the Boost converter in CCM (III) Summary iOiO t t t iSiS iDiD iLiL dT T t iLiL t Driving signal vDvD vOvO i L_avg = i g_avg = i O /(1-d) = v o /[R L (1-d)] v O = v g /(1-d) (always v O > v g ) i S_avg = d·i L_avg = d·v o /[R L (1-d)] i D_avg = i O  i L = v g dT/L i L_peak = i L_avg +  i L /2 = i L_avg + v g dT/(2L) v Smax = v Dmax = v O i S_peak = i D_peak = i L_peak vSvS + - vDvD + - C vgvg iLiL iSiS L S iDiD D RLRL vOvO iOiO + - vLvL +- igig iCiC SEA_uniovi_CC1_21

23. 23 Steady-state analysis of the Buck-Boost converter in CCM (I) t t t t iSiS iDiD iLiL Driving signal dT T Can we obtain either v O v g ?  Buck-Boost converter iLiL  From Faraday’s law:  i L = v g dT/L + - C D vgvg iLiL iSiS L S iDiD RLRL iOiO vOvO - + igig vLvL + - S on, D off, during dT Charging stage iLiL vgvg L vLvL + - igig S off, D on, during (1-d)T iOiO RLRL vOvO C - + iLiL L vLvL + - Discharging stage + - SEA_uniovi_CC1_22

24. 24 Steady-state analysis of the Buck-Boost converter in CCM (II) Step 2 and 2 (bis): Average values  KCL applied to Node1 yields: i D - i C - i O = 0 i D_avg - i C_avg - i O = 0 Therefore: i D_avg = i L_avg (1-d) = i O = v O /R L  Volt·second balance over L: v g dT - v O (1-d)T = 0 Therefore: v O = v g d/(1-d)  Average value of i C : i C_avg = 0 Step 3: Average KCL and KVL: Step 4: Power balance: i g_avg = i S_avg = i O v O /v g = i O d/(1-d) Node1 + - C D vgvg iLiL iSiS L S iDiD RLRL iOiO vOvO - + igig vLvL + - iCiC dT vgvg T Driving signal t t t vLvL iDiD i D_avg iLiL -v O SEA_uniovi_CC1_23

25. 25 Steady-state analysis of the Buck-Boost converter in CCM (III) Summary i L_avg = i D_avg /(1-d) = i O /(1-d) = v o /[R L (1-d)] v O = v g d/(1-d) (both v O v g ) i S_avg = i g_avg = d·i L_avg = d·v o /[R L (1-d)] i D_avg = i O  i L = v g dT/L i L_peak = i L_avg +  i L /2 = i L_avg + v g dT/(2L) v Smax = v Dmax = v O + v g i S_peak = i D_peak = i L_peak iOiO t t t iSiS iDiD iLiL dT T t iLiL t Driving signal vDvD v O + v g + - C D vgvg iLiL iSiS L S iDiD RLRL iOiO vOvO - + igig vLvL + - vDvD - + vSvS - + SEA_uniovi_CC1_24

26. 26 Common issues in basic DC/DC converters (I) RLRL vgvg vOvO S C L D + - + - Buck + - C vgvg L S D RLRL vOvO + - Boost + - C D vgvg L S RLRL vOvO + - Buck-Boost Complementary switches + inductor vgvg RLRL vOvO + - + - C L D S d 1-d Voltage source The inductor is an energy buffer to connect two voltage sources SEA_uniovi_CC1_25

27. 27 Common issues in basic DC/DC converters (II) + - C vgvg L S D RLRL vOvO + - Boost vOvO RLRL vgvg vOvO S C L D + - + - Buck vgvg + - C D vgvg L S RLRL vOvO + - Buck- Boost v O + v g Diode turn-off  The diode turns off when the transistor turns on  The diode reverse recovery time is of primary concern evaluating switching losses  Schottky diodes are desired from this point of view  In the range of line voltages, SiC diodes are very appreciated SEA_uniovi_CC1_26

28. 28 Comparing basic DC/DC converters (I) Generalized study as DC transformer (I) DC Transformer vgvg iOiO i g_avg RLRL vOvO + - 1:N + - C vgvg L S D RLRL vOvO iOiO + - igig Boost + - C D vgvg L S RLRL iOiO vOvO + - igig Buck-Boost RLRL vgvg vOvO S iOiO igig C L D + - + - Buck  Buck: N= d (only v O < v g )  Boost: N= 1/(1-d) (only v O > v g )  Buck-Boost: N= -d/(1-d) (both v O v g ) SEA_uniovi_CC1_27

29. 29 Comparing basic DC/DC converters (II) Generalized study as DC transformer (II)  Buck: i g_avg = i O N = i O d  Boost: i g_avg = i O N = i O /(1-d)  Buck-Boost: i g_avg = i O N = - i O d/(1-d) DC Transformer vgvg iOiO i g_avg RLRL vOvO + - 1:N i g_avg = i O N = i O d/(1-d) SEA_uniovi_CC1_28

30. 30 Comparing basic DC/DC converters (III) Electrical stress on components (I)  Buck: v Smax = v Dmax = v g i S_avg = i g_avg i L_avg = i O i D_avg = i L_avg - i S_avg vgvg igig iDiD D vDvD + - S iSiS vSvS + - RLRL vOvO iOiO + - DC/DC converter  Boost: v Smax = v Dmax = v O i L_avg = i g_avg i D_avg = i O i S_avg = i L_avg - i D_avg  Buck-Boost: v Smax = v Dmax = v O + v g i S_avg = i g_avg i D_avg = i O i L_avg = i S_avg + i D_avg SEA_uniovi_CC1_29

31. 31 Comparing basic DC/DC converters (IV) Example of electrical stress on components (I) v S_max = v D_max = 100 V i S_avg = i D_avg = 1 A i L_avg = 2 A FOM VA_S = FOM VA_D = 100 VA RLRL S C L D + - + - 50 V 100 V 2 A 1 A (avg) 100 W Buck, 100% efficiency + - C D L S RLRL - + 50 V 100 V 2 A 1 A (avg) 100 W Buck-Boost, 100% efficiency v S_max = v D_max = 150 V i S_avg = 1 A i D_avg = 2 A i L_avg = 3 A FOM VA_S = 150 VA FOM VA_D = 300 VA  Higher electrical stress in the case of Buck- Boost converter  Therefore, lower actual efficiency SEA_uniovi_CC1_30

32. 32 Comparing basic DC/DC converters (V) Example of electrical stress on components (II) v S_max = v D_max = 50 V i S_avg = i D_avg = 2 A i L_avg = 4 A FOM VA_S = FOM VA_D = 100 VA + - C L S D RLRL + - 50 V 25 V 2 A 4 A (avg) 100 W Boost, 100% efficiency + - C D L S RLRL - + 50 V 25 V 2 A 4 A (avg) 100 W Buck-Boost, 100% efficiency v S_max = v D_max = 75 V i S_avg = 4 A i D_avg = 2 A i L_avg = 6 A FOM VA_S = 300 VA FOM VA_D = 150 VA  Higher electrical stress in the case of Buck- Boost converter  Therefore, lower actual efficiency SEA_uniovi_CC1_31

33. 33 Comparing basic DC/DC converters (VI)  Price to pay for simultaneous step-down and step-up capability: Higher electrical stress on components and, therefore, lower actual efficiency  Converters with limited either step-down or step-up capability: Lower electrical stress on components and, therefore, higher actual efficiency SEA_uniovi_CC1_32

34. 34 Comparing basic DC/DC converters (VII) 300 W Boost, 98% efficiency + - C L S D RLRL + - 60 V 50 V 5 A 6.12 A (avg) 1.12 A (avg) Example of power conversion between similar voltage levels based on a Boost converter Very high efficiency can be achieved!!! v S_max = v D_max = 60 V i S_avg = 1.12 A i D_avg = 5 A i L_avg = 6.12 A FOM VA_S = 67.2 VA FOM VA_D = 300 VA SEA_uniovi_CC1_33

35. 35 Comparing basic DC/DC converters (VIII) The opposite case: Example of power conversion between very different and variable voltage levels based on a Buck- Boost converter High efficiency cannot be achieved!!! 300 W Buck-Boost, 75% efficiency + - C D L S RLRL - + 60 V 20 - 200 V 5 A 20 - 2 A (avg) v S_max = v D_max = 260 V i S_avg_max = 20 A i D_avg_max = 5 A i L_avg = 25 A FOM VA_S_max = 5200 VA FOM VA_D = 1300 VA Remember previous example: FOM VA_S = 67.2 VA FOM VA_D = 300 VA SEA_uniovi_CC1_34

36. 36 Comparing basic DC/DC converters (IX) One disadvantage exhibited by the Boost converter: The input current has a “direct path” from the input voltage source to the load. No switch is placed in this path. As a consequence, two problems arise:  Large peak input current in start-up  No over current or short-circuit protection can be easily implemented (additional switch needed) Buck and Buck-Boost do not exhibit these problems + - C vgvg L S D RLRL vOvO + - Boost SEA_uniovi_CC1_35

37. 37 Synchronous rectification (I)  To use controlled transistors (MOSFETs) instead of diodes to achieve high efficiency in low output-voltage applications  This is due to the fact that the voltage drop across the device can be lower if a transistor is used instead a diode  The conduction takes place from source terminal to drain terminal  In practice, the diode (Schottky) is not removed S L D S1S1 L S2S2 S1S1 L S2S2 i device v device Diode MOSFET SEA_uniovi_CC1_36

38. 38 Synchronous rectification (II)  In converters without a transformer, the control circuitry must provide proper driving signals  In converters with a transformer, the driving signals can be obtained from the transformer (self-driving synchronous rectification)  Nowadays, very common technique with low output-voltage Buck converters S1S1 L S2S2 Feedback loop - V ref AvAv vOvO PWM Q Q’ RLRL vgvg vOvO C L + - + - Synchronous Buck S1S1 S2S2 D SEA_uniovi_CC1_37

39. 39 Input current and current injected into the output RC cell (I) vgvg igig iDiD D vDvD + - S iSiS vSvS + - RLRL vOvO + - DC/DC converter + - C i RC t Desired current igig t i RC Desired current  If a DC/DC converter were an ideal DC transformer, the input and output currents should also be DC currents  As a consequence, no pulsating current is desired in the input and output ports and even in the current injected into the RC output cell SEA_uniovi_CC1_38

40. 40 Input current and current injected into the output RC cell (II) t igig Noisy RLRL vgvg vOvO S i RC igig C L D + - + - Buck t Low noise i RC + - C vgvg L S D RLRL vOvO + - Boost igig i RC Low noise t igig t Noisy i RC vOvO + - + - C D vgvg L S RLRL Buck-Boost igig i RC t Noisy igig t i RC SEA_uniovi_CC1_39

41. 41 Input current and current injected into the output RC cell (III) RLRL vgvg vOvO S i RC igig C L D + - + - Buck CFCF LFLF + - + - CFCF vgvg L S D Boost igig i RC RLRL vOvO + - C LFLF + - igig + - CFCF D L S Buck-Boost RLRL vOvO - + C LFLF - + vgvg CFCF LFLF + - Filter Adding EMI filters SEA_uniovi_CC1_40

42. 42 Four-order converters (converters with integrated filters) RLRL vgvg vOvO + - igig iSiS iDiD L1L1 C2C2 S D i L2 L2L2 C1C1 + - v C1 SEPIC RLRL vgvg vOvO + - igig iSiS iDiD L1L1 C2C2 S D i L2 L2L2 C1C1 + - v C1 Cuk RLRL vgvg vOvO + - iSiS iDiD L1L1 C2C2 S D i L2 L2L2 C1C1 + - i L1 v C1 Zeta  Same v O /v g as Buck-Boost  Same stress as Buck-Boost  v C1 = v g  Filtered input  Same v O /v g as Buck-Boost  Same stress as Buck-Boost  v C1 = v g + v O  Filtered input and output  Same v O /v g as Buck-Boost  Same stress as Buck-Boost  v C1 = v O  Filtered output SEA_uniovi_CC1_41

43. 43 DC/DC converters operating in DCM (I)  Only one inductor in basic DC/DC converters  The current passing through the inductor decreases when the load current decreases (load resistance increases) vgvg igig D S RLRL vOvO iOiO + - DC/DC converter L iLiL T dT t t iLiL Driving signal i L_avg  Buck: i L_avg = i O  Boost: i L_avg = i O /(1-d)  Buck-Boost: i L_avg = i S_avg + i D_avg = di O /(1-d) + i O = i O /(1-d) SEA_uniovi_CC1_42

44. 44  When the load decreases, the converter goes toward Discontinuous Conduction Mode (DCM) i L_avg t iLiL R L_1 t iLiL R L_2 > R L_1 i L_avg iLiL t R L_crit > R L_2 i L_avg Decreasing load It corresponds to R L = R L_crit Boundary between CCM and DCM Operation in CCM DC/DC converters operating in DCM (II) SEA_uniovi_CC1_43

45. 45 What happens when the load decreases below the critical value? iLiL t R L_crit i L_avg Decreasing load  DCM starts if a diode is used as rectifier  If a synchronous rectifier (SR) is used, the operation depends on the driving signal  CCM operation is possible with synchronous rectifier with a proper driving signal (synchronous rectifier with signal almost complementary to the main transistor) iLiL t R L_3 > R L_crit i L_avg CCM w. SR iLiL t R L_3 > R L_crit i L_avg DCM w. diode DC/DC converters operating in DCM (III) SEA_uniovi_CC1_44

46. 46 Remember: i L_avg = i O (Buck) or i L_avg = i O /(1-d) (Boost and Buck-Boost)  For a given duty cycle, lower average value (due to the negative area)  lower output current for a given load  lower output voltage iLiL t i L_avg R L > R L_crit DCM w. diode  For a given duty cycle, higher average value (no negative area)  higher output current for a given load  higher output voltage iLiL t R L > R L_crit CCM w. SR i L_avg The voltage conversion ratio v O /v g is always higher in DCM than in CCM (for a given load and duty cycle) DC/DC converters operating in DCM (IV) SEA_uniovi_CC1_45

47. 47 How can we get DCM (of course, with a diode as rectifier) ? t iLiL t iLiL t iLiL After decreasing the inductor inductance After decreasing the switching frequency After decreasing the load (increasing the load resistance) DC/DC converters operating in DCM (V) SEA_uniovi_CC1_46

48. 48 DC/DC converters operating in DCM (VI) Three sub-circuits instead of two:  The transistor is on. During d·T  The diode is on. During d’·T  Both the transistor and the diode are off. During (1-d- d’)T t iLiL t i L_avg vLvL T d·T t d’·T + - iDiD t i D_avg -v O vgvg Driving signal + - C D vgvg iLiL iSiS L S iDiD RLRL iOiO vOvO - + igig vLvL + - iLiL vgvg L vLvL + - igig During d·T iOiO RLRL vOvO C - + iLiL L vLvL + - + - During d’·T iLiL L vLvL + - During (1-d-d’)T Example: Buck-Boost converter SEA_uniovi_CC1_47

49. 49 DC/DC converters operating in DCM (VII) Voltage conversion ratio v O /v g for the Buck-Boost converter in DCM iLiL vgvg L vLvL + - igig During d·T iOiO RLRL vOvO C - + iLiL L vLvL + - + - During d’·T From Faraday’s law: v g = Li L_max /(dT) And also: v O = Li L_max /(d’T) Also: i D_avg = i L_max d’/2, i D_avg = v O /R And finally calling M = v O /v g we obtain: M =d/(k) 1/2 where k =2L/(RT) t iLiL t i L_avg vLvL T d·T t d’·T + - iDiD t i D_avg -v O vgvg Driving signal i L_max SEA_uniovi_CC1_48

50. 50  Due to being in DCM: M = v O /v g = d/(k) 1/2, where: k = 2L/(RT)  Due to being in CCM: N = v O /v g = d/(1-d)  Just on the boundary: M = N, R = R crit, k = k crit  Therefore: k crit = (1-d) 2  The converter operates in CCM if: k > k crit  The converter operates in DCM if: k < k crit DC/DC converters operating in DCM (VIII) The Buck-Boost converter just on the boundary between DCM and CCM iLiL t R L = R L_crit i L_avg SEA_uniovi_CC1_49

51. 51 N = d 2 M = 1 + 4k d2d2 k crit = (1-d) k crit_max = 1 Buck d M = k d N = 1-d k crit = (1-d) 2 k crit_max = 1 Buck-Boost 2 M = 1 + 4d 2 k 1 N = 1-d k crit = d(1-d) 2 k crit_max = 4/27 Boost DC/DC converters operating in DCM (IX) Summary for the basic DC/DC converter k = 2L/(RT) SEA_uniovi_CC1_50

52. 52 CCM versus DCM DC/DC converters operating in DCM (X) t t t iSiS iDiD iLiL dT T t t Driving signal vDvD i L_avg t t t iSiS iDiD iLiL dT T t t Driving signal vDvD i L_avg - Lower conduction losses in CCM (lower rms values) - Lower losses in DCM when S turns on and D turns off - Lower losses in CCM when S turns off - Lower inductance values in DCM (size?) SEA_uniovi_CC1_51

53. 53 v i = n i d  /dt  =  B -  A = (v i /n i )·dt B A From Faraday’s law: In steady-state: (  ) in a period  = 0 Achieving galvanic isolation in DC/DC converters (I) (v i /n i ) avg = 0 And therefore: Volt·second balance: If all the voltages are DC voltages, then:  CCM: dT(V 1 /n 1 ) – (1-d)T(V 2 /n 2 ) = 0  DCM: dT(V 1 /n 1 ) –d’T(V 2 /n 2 ) = 0 vgvg Circuit in steady- state n 1 :n 2 v1v1 + - v2v2 + - SEA_uniovi_CC1_52 - A two-winding magnetic device is needed - The volt·second balance in the case of magnetic devices with two windings must be used

54. 54 Achieving galvanic isolation in DC/DC converters (II) n 1 :n 2 Model 1: Circuit Theory element n 1 :n 2 L m1 Model 2: Magnetic transformer with perfect coupling n 1 :n 2 L m1 L l1 L l2 Model 3: Magnetic transformer with real coupling Model 1 Model 2 Transformer models At least the magnetizing inductance must be taken into account analyzing DC/DC converters SEA_uniovi_CC1_53

55. 55 Achieving galvanic isolation in DC/DC converters (III) n 1 :n 2 L m1 Where must we place the transformer? vgvg igig vDvD D + - vSvS S + - RLRL vOvO iOiO + - DC/DC converter In a place where the average voltage is zero SEA_uniovi_CC1_54

56. 56 Achieving a Buck converter with galvanic isolation (I) RLRL vgvg vOvO S C L D + - + - Buck n 1 :n 2 L m1 No place with average voltage equal to zero RLRL vgvg vOvO S C L D + - + - New node with possible zero average voltage vgvg S RLRL vOvO C L D1D1 + - + - D2D2 S off It does not work!! S on SEA_uniovi_CC1_55

57. 57 Achieving a Buck converter with galvanic isolation (II) v extra n3n3 D2D2 n 1 :n 2 L m1 vgvg RLRL vOvO C L + - + - D1D1 S on S off S n 1 :n 1 :n 2 L m1 vgvg RLRL vOvO C L + - + - D1D1 D2D2 D3D3 Final implementation: the Forward converter Standard design: v extra = v g n 3 = n 1 A circuit to apply a given DC voltage across L m1 when S is off SEA_uniovi_CC1_56

58. 58 The Forward converter S n 1 :n 1 :n 2 L m1 vgvg RLRL vOvO C L + - + - D1D1 D2D2 D3D3 As the Buck converter replacing v g with v g n 2 /n 1 Transformer magnetizing stage vgvg L m1 vLvL + - i m1 iOiO iLiL RLRL v g n 2 /n 1 vOvO C L + - Inductor magnetizing stage S & D 2 on, D 1 & D 3 off, during dT D 3 on, during d’T Transformer reset stage vgvg L m1 vLvL + - i m1 iOiO iLiL RLRL vOvO C L + - Inductor demagnetizing stage during (1-d)T S & D 2 off, D 1 on, v O = dv g n 2 /n 1 v Smax = 2 v g d max = 0.5 (reset transformer) SEA_uniovi_CC1_57

59. 59 Achieving a Buck-Boost converter with galvanic isolation (I) n 1 :n 2 L m1 There is a place with average voltage equal to zero: the inductor RLRL vOvO C - + - + D vOvO - + + - C D vgvg L S RLRL Buck- Boost vgvg S L S off S on n 1 :n 2 L RLRL vOvO C - + - + D vgvg S Inductor and transformer integrated into only one magnetic device (two-winding inductor) SEA_uniovi_CC1_58

60. 60 Achieving a Buck-Boost converter with galvanic isolation (II) n 1 :n 2 L RLRL vOvO C - + - + D vgvg S Final implementation: the Flyback converter S n 1 :n 2 vgvg RLRL vOvO C + - + - D L1L1 L2L2 S off, D on, during (1-d)T iOiO RLRL vOvO C - + v L n 2 /n 1 + - Discharging stage + - L2L2 S on, D off, during dT Charging stage vgvg L1L1 vLvL + - igig Two-winding inductor SEA_uniovi_CC1_59

61. 61 The Flyback converter S n 1 :n 2 vgvg RLRL vOvO C + - + - D L1L1 L2L2 Analysis in steady-state in CCM  Volt·second balance: dTv g /n 1 - (1-d)Tv O /n 2 = 0  v O = v g (n 2 /n 1 )·d/(1-d)  Therefore, the result is the same as Buck-Boost converter replacing v g with v g n 2 /n 1  v Smax = v g + v O n 1 /n 2  v Dmax = v g n 2 /n 1 + v O  Very simple topology  Useful for low-power, low-cost converters  Critical “false transformer” (two-winding inductor) design SEA_uniovi_CC1_60

62. 62 Achieving other converters with galvanic isolation (I) + - C vgvg L S D RLRL vOvO + - Boost It is not possible with only one transistor!! RLRL vgvg vOvO + - L1L1 C2C2 S D L2L2 C1C1 + - SEPIC n 1 :n 2 RLRL VgVg VOVO + - L1L1 C3C3 S D L2L2 C1C1 + - C2C2 + - Cuk  Zeta converter is also possible  v O = v g (n 2 /n 1 )d/(1-d)  v Smax = v g + v O n 1 /n 2  v Dmax = v g n 2 /n 1 + v O Like the Flyback converter SEA_uniovi_CC1_61