1. A Quad-Channel 3.125Gb/s/ch Serial-Link Transceiver with Mixed-Mode Adaptive Equalizer in 0.18µm CMOS Authors : Jeongsik Yang, Jinwook Kim, Sangjin Byun, Cormac Conroy,Beomsup Kim Provided By: SAEID MEHRMSNEDH

2. Outline Why serial link? Transceiver Architecture Current Mode Logic Multiplexer Equalization Data recovery Conclusion

3. Why serial link? Less Complexity Using Fully Differential Signaling Digital Data as an analog signal Equalization Methods Data recovery Asynchrony

4. Transceiver Architecture

5. Current Mode Logic More Speed Noise Immunity No bad effect on supply Constant current High Power consumption

6. Input Multiplexer

7. Why Equalization? Bandwidths Limitation of channel Channel Distortion If channel transfer function is H(S) we can add H -1 (S) in signal path Avoiding inter symbol interference

8. Equalizer Circuits Equalization at Receiver Lower power consummation Adaptive methods (LMS) Farjadrad methods

9. Clock Data Recovery

10. CDR Result

11. Results

12. Conclusion Better Input multiplexer Input Equalization Delay Immune CDR Achieving good power consumption characteristic (.18 W per channel)