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555 Timer Monostable ©Paul Godin Updated February 2008.

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Presentation on theme: "555 Timer Monostable ©Paul Godin Updated February 2008."— Presentation transcript:

1 555 Timer Monostable ©Paul Godin Updated February 2008

2 555 as a Monostable ◊The 555 timer can also be configured as a monostable. ◊The 555 Monostable has interesting characteristics that may be used in specific applications. 555mono.2

3 Monostable Multivibrator Operation of the 555 Timer 555mono.3

4 Monostable The Trigger is active low. Input must be below 1/3 Vcc. The RC controls a charge cycle only. The Trigger must be brought high to allow the latch to reset. Animation 555mono.4

5 Timing Diagram Tw The Trigger is active low. Input trigger Output pulse Output pulse created when input trigger voltage is less than 1/3 Vcc If the trigger is held low beyond calculated pulse width, the output pulse follows the input trigger 555mono.5

6 Monostable Filter Cap 0.01μF Calculated Values 555mono.6

7 Calculations: Monostable Notes: The value 1.1 is a k-factor associated with the 555 timer. The trigger is active-low (not edge-triggered), and must be brought high before the end of the pulse width. Tw 555mono.7

8 EWB and Multisim ◊The 555 timer as a monostable in EWB and Multisim is problematic. The simulation tends to run too slowly and the application may crash. ◊There seems to be no way around this problem. Recommend multiple saves with different file names so that you may revert if needed. 555mono.8

9 Sample Monostable Calculation ◊Design a Monostable that produces a 5S pulse. Use a 100F capacitor. 555mono.9

10 Design Exercises 555mono.10

11 Design Exercise 1.Using a 555 timer, design a monostable with an output pulse of 4 seconds. Use a 100μF capacitor. What happens if you leave the trigger in an output low state? 555mono.11

12 Animated Slide The following slides contain animations to demonstrate the operations of: 555 as a monostable 555mono.12

13 Monostable 0 + < - 1 0 0 Vc Wait-state. The transistor discharges the Capacitor 0 A low is applied to the trigger input. The comparator provides a logic high; the latch is set. 1 0 + > - 1 Q’ goes low; Q high. The transistor is “off”. Cap charges. +> - Capacitor voltage > 2/3 Vcc. High comparator output high. 1 Latch reset. Q’ logic high. Capacitor discharges, waits. 1 0 Animated 555mono.13

14 ©Paul R. Godin prgodin ° @ gmail.com 555mono.14 END


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