1. Why do we put the micro in microelectronics?

2. Why Micro? 1.Lower Energy and Resources for Fabrication 2.Large Arrays 3.Minimally Invasive 4.Disposable 5.Smaller Time Scales 6.Lower Cost What about the Physics?

3. Why silicon?

4. 4 Silicon Si semiconductor 5 silicon atoms in a unit cell Diamond lattice Covalent bonds 14 electrons 4 valence electrons Silicon molecules: http://www.eere.energy.gov/pv/simolecule.html 0.543 nm0.235 nm Si electronsholes

5. Cu 2 Mg Al, Cu, Au, … CdTe Si Crystalline Materials Regular arrangement of atoms with long range order Many Properties Depend on Atomic Structure

6. Single Crystals Properties are: Anisotropic (they depend on crystallographic direction)

7. What is Isotropy? Isotropic – Does not have any dependence on the crystallographic orientation Anisotropic – Depends upon the crystallographic orientation

8. Polycrystalline What are grains? individual crystals that have nucleated with a random orientation. Properties are: Isotropic (same in all directions)

9. Crystallographic texture: Columnar grains grow with a preferred orientation, but are random in-plane. Properties are: Isotropic (in-plane) and Anisotropic (out-of-plane) [011] Especially important in thin films and MEMS - Polysilicon - LIGA Ni

10. Atomic Packing: Amorphous glasses Loss of long range order Properties are: Isotropic (same in all directions)

11. Atomic packing: polymers HH H HHHH || ||||| +Energy C = C +Energy -> - C -C -C -C -C - ||||||| HHH HHHH + E Ethylene + E -> Polyethylene

12. Atomic packing: polymers Tangled long chain molecules of C and H - “think spaghetti” Properties are: Isotropic (same in all directions) Polyethylene

13. Crystalline Silicon

15. Crystallographic planes : Miller Index: Plane (100) Type {100} [100] [001] [010]

16. Crystallographic planes : Miller Index: Plane (110) [100] [001] [010]

17. Crystallographic planes : Miller Index: Plane: (111) [100] [001] [010]

18. Silicon wafers: IC standard wafers: {111} n-type {111} P-type {100} n-type {100} p-type Primary flat Secondary flat Secondary flat Secondary flat Primary flat Primary flat Primary flat

19. Silicon wafers: Si wafers for micromachining: Primary flat Primary flat  3  or [010] [001] {100}{110} Better for diaphragmsEasier to cleave

20. Silicon Crystal Growth The manufacture of a silicon crystal ingot suitable for CMOS processing requires extremely high temperatures and exact control of impurity concentrations such as phosphorus and boron. A high-temperature/high-purity crystal puller is used http://www.youtube.com/watch?v=xftnhfa-Dmo&feature=related

21. Czochralski Crystal Puller A 2-3 mm diameter silicon 'seed' crystal is rotated and lowered into a bath of molten Si (T>1420º C). The seed is then withdrawn and some of the melt 'freezes' onto the seed. At this point there are large stresses between the cool center of the crystal and the heated exterior  dislocation formation. By rapidly pulling the seed out of the melt a thin 'necked' region forms. The dislocations move to the surface of the neck and no longer influence the crystal growth. The final crystal of ingot of silicon has a low dislocation density.

22. First Transistor 1948 Shockley, Bardeen & Brattain: Bell Labs

23. Integrated Circuits in 1958 Jack Kilby at Texas Instruments

24. Integrated Circuits in 1962 RTL Logic (Noyce and Hoerni)

25. Integrated Circuits in 1965 Operational Amplifier, Fairchild ua 709

26. Integrated Circuits in 1991 Power PC, AIM (Apple-IBM-Motorola Alliance)

27. Today’s Microelectronics & MEMS Analog Devices, Accelerometers and Gyroscopes

28. Decrease in Minimum Feature Size with Time (Moore’s law)

29. Clean Room Classification English system: Numerical designation of the class is maximum allowable number of particles that are 0.5  m and larger per cubic foot of air. Metric system: Numerical designation of the class is taken from the Logarithm (base 10) of the maximum allowable number of particles that are 0.5  m and larger per cubic foot of air IC is very sensitive to particles. It usually requires Class 10 or better MEMS is more robust to particulates

30. Fabrication Process Architecture Mask Design Photolithography Photoresist Silicon Oxidation Wet Etching Thin Film Deposition Packaging Testing

31. Microfabrication Silicon Oxidation Photoresist Deposition Masking and Exposure Figures from May and Sze

32. Photoresist Development Si02 etching Photoresist Cleaning Doping Metallization Patterning Figures from May and Sze

33. Dry Oxidization : Si (solid) + O 2 (gas)  SiO 2 (solid) Wet Oxidization: Si (solid) + 2H 2 O (gas)  SiO 2 (solid) + 2H 2 (gas) Thermal Oxidization

34. Photolithography: Pattern Transfer The remaining image after pattern transfer can be used as a mask for subsequent process such as etching, ion implantation, and deposition.

35. Doped Silicon N- doped P- doped Silicon molecules: http://www.eere.energy.gov/pv/simolecule.html Si P B free electrons bound electrons holes

36. Diffusion Constant source – High surface concentrations, shallow, "deposition“ Limited source – Low surface concentrations, deep, "drive-in"

37. Ion-implantation

38. Thermal Evaporator Pump down to 1  torr ( 1 torr = 1 mmHg) Place wafers upside down to reduce particles Heat sources until white hot Low pressure = long mean-free- path (i.e., directional deposition) Use shutter for better timing Thin Film Deposition

39. http://www.youtube.com/watch?v=aWVywhzuHnQ&feature=related

40. LIGA: electroplating nickel www.me.mtu.edu/~microweb

41. http://mems.sandia.gov/gallery/images.html