1. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 1 ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2015 Introduction Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. Course Webpage http://www.eng.auburn.edu/~vagrawal/ COURSE/E6200_Fall15/course.html http://www.eng.auburn.edu/~vagrawal/ COURSE/E6200_Fall15/course.htmlOr, Go to professor’s webpage http://www.eng.auburn.edu/~vagrawal/ http://www.eng.auburn.edu/~vagrawal/ Click on ELEC5200-001/6200-001 Computer Architecture and Design, MWF 11AM, Broun 235. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 2

3. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 3 Course Organization Text book: D. A. Patterson and J. L. Hennessy, Computer Organization & Design, the Hardware/Software Interface, Fifth Edition, Morgan Kaufman (Elsevier), 2014, ISBN 978-0- 12-407726-3. Instructor: Vishwani D. Agrawal, Broun 323, x41853, vagrawal@eng.auburn.edu. vagrawal@eng.auburn.edu Graduate Assistant: Hunter Thorington, hlt0001@auburn.edu, Broun xxx, consulting hours to be posted. hlt0001@auburn.edu Classroom: Broun 235, MWF 11:00-11:50AM. Lab: Broun 320.

4. Author of the Text Book Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 4 Q&A: RISC and Reward, Communications of the ACM, Volume 57, No. 3, pp. March 2014, pages 112 and 111.

5. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 5 Author of the Text Book

6. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 6 Student Performance Evaluation Homework (25%): 1 per week, most weeks. Two Class Tests (25%): Test 1, Friday, Sep 18, 2015, 11:00-11:50AM, Broun 235. Test 2, Wednesday, Oct 7, 2015, 11:00-11:50AM, Broun 235. CPU Design Project (25%). Final Exam (25%): Wednesday, Dec 9, 2015, 12:00 – 2:30PM, Broun 235. Class Presentation, if time permits, on assigned topic by ELEC6200 Students; “Satisfactory” grade necessary; attendance necessary for ELEC5200 students.

7. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 7 Course Objective Learn what a digital computer contains and how it works. Learn design concepts of a modern computer. Gain design experience (through project).

8. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 8 The Concept of a Computer Application software Programs user writes and runs Hardware Systems software Operating system compiler assembler User

9. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 9 Software Application software, a program in C: swap (int v[ ], int k) {int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } MIPS binary machine code: 00000000101000010000000000011000 00000000000110000001100000100001 10001100011000100000000000000000 10001100111100100000000000000100 10101100111100100000000000000000 10101100011000100000000000000100 00000011111000000000000000001000 CompilerAssembler Application software Hardware Systems software See pages 122-123 MIPS compiler output, assembly language program: swap; muli$2,$5, 4 add$2,$4, $2 lw$15, 0 ($2) lw$16, 4 ($2) sw$16, 0 ($2) sw$15, 4 ($2) jr$31

10. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 10 The Hardware of a Computer Control Datapath Memory Central Processing Unit (CPU) or “processor” Input Output FIVE EASY PIECES Application software Hardware Systems software

11. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 11 Instruction Set Architecture (ISA) A set of assembly language instructions (ISA) provides a link between software and hardware. Given an instruction set, software programmers and hardware engineers work more or less independently. ISA is designed to extract the most performance out of the available hardware technology. Instruction set SoftwareHardware Application software Hardware Systems software

12. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 12 ISA Defines registers Defines data transfer modes between registers, memory and I/O Types of ISA: RISC, CISC, VLIW, Superscalar Examples: –IBM370/X86/Pentium/K6 (CISC) –PowerPC (Superscalar) –Alpha (Superscalar) –MIPS (RISC and Superscalar) –Sparc (RISC), UltraSparc (Superscalar)

13. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 13 Computer Architecture Architecture: System attributes that have a direct impact on the logical execution of a program Architecture is visible to a programmer: –Instruction set –Data representation –I/O mechanisms –Memory addressing

14. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 14 Computer Organization Organization: Physical details that are transparent to a programmer, such as –Hardware implementation of an instruction –Control signals –Memory technology used Example: System/370 architecture has been used in many IBM computers, which widely differ in their organization.

15. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 15 Architecture and Organization Software Programmers Hardware Engineers ISA

16. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 16 CPU Design Project Design and implementation of a processor: –Define instruction set –Design datapath and control hardware –Implement hardware in FPGA –Verify

17. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 17 Research and Developments of Continuing Interest Instruction level parallelism (ILP) Multi-core systems and chip multi-processing (CMP) Processors Inter-processor communication Memory organization Operating system Programming languages Computing algorithms Energy efficiency and low power design Embedded systems Quantum computing, biological computing,...

18. Fall 2015, Aug 17 ELEC 5200-001/6200-001 Lecture 1 18 Summary A computer processes digital data. A user solves problems by writing and running programs written in a high-level programming language like C. Inside computer, system programs called compiler and assembler break the user program down into assembly code (instruction set) and then into binary machine code. The machine code is processed by the 5-piece hardware (control unit, datapath, memory, input and output) to obtain the desired result. Readings on architecture (posted at course website): –L. Hoffmann, “Q&A: RISC and Reward (An Interview with David Patterson),” Comm. ACM, vol. 57, no. 3, pp. 112, 111, March 2014. –S. Borkar and A. A. Chen, “The Future of Microprocessors,” Comm. ACM, vol. 54, no. 5, pp. 67-77, May 2011.