1. Introduction to Controlling the Output Power of a Transistor Stage A load network will be designed to maximize the output power obtainable from the Mitsubishi MGF0909A power transistor. The gain associated with maximum power is high enough not to be a concern in this case. Two solutions to the matching problem will be considered. The network selected will be expanded to allow for feeding the required dc to the drain of the transistor. Care will be taken to model the effects of the high Q capacitors added accurately. Changes will also be made to the matching network to reduce the expected discontinuity effects and the network will be optimized to restore the power performance.

2. The circuit as set up in the previous example.

3. The CIL Command is selected on the left (Synthesis Toolbar) to control the output power of the transistor.

4. The matching network required will be inserted at the position shown.

5. The CIL Wizard has been launched.

6. The passband can be modified on this page.

7. The option to control the output power has been selected.

8. The S-parameter normalization resistance can be changed here.

9. The actual output power and the operating power gain are of interest. Power contours will be generated.

10. The power targeted must be specified on this page

11. The Display Contours Command has been selected.

12. The zoom slider was used to expand the view around the optimum power load.

13. The maximum power is targeted. Additional contours can be displayed at 1dB and 2dB down from the optimum.

14. The performance around the power contour targeted is tabulated at 2.075GHz. The optimum point on the contour is high-lighted and can be changed at this point.

15. The terminations to be presented by the matching network in order to realize the power targeted are tabulated here.

16. The Display Impedance Radio Button was selected to list the impedance required for maximum output power (the power targeted).

17. The default name assigned to the data file of the matching problem to be solved.

18. The final page of the Power Contour Wizard.

19. The Impedance-Matching Module has been activated. The problem will be solved with a non-commensurate microstrip network.

20. The Distributed Network Wizard will be launched to set the constraints on the microstrip networks to be synthesized.

21. The general form of the non-commensurate networks allowed is displayed.

22. The specifications of the substrate to be used.

23. The specifications of the via holes to be used.

24. The parasitic inductance for any capacitors to be used (0603).

25. Double stubs and stepped main-line sections will be allowed.

26. The line widths and the stub separation to be used.

27. A rendering of the specifications made.

28. The parasitics associated with the T-junctions associated with the specifications made.

29. The default gaps to be used for any capacitors or inductors.

30. The pad size to be used for any series capacitors.

31. The electrical line length of the pads should be kept short.

32. The steps of the wizard have been completed.

33. The changes made must be saved before the synthesis cycle is started.

34. The Synthesis Command is selected.

35. The synthesized solutions can be optimized for the best active performance.

36. The optimization target selected for the output power is the same as before.

37. The gain targeted is also the same as before.

38. Different weights can be assigned to the output power and the gain targeted.

39. The best solution (smallest error) obtained with the specifications made.

40. The impedance presented to the circuit by the selected matching network.

41. An exploded view of the power termination.

42. The command to display the active performance associated with the selected solution.

43. The output power and gain associated with the selected solution.

44. The artwork of the solution.

45. The solution will be closed and alternatives will be investigated.

46. The Specifications | Topology Command will be selected.

47. The option not to use any series capacitors will be explored.

48. Solutions without any series capacitors will be synthesized.

49. The option to optimize the active performance will be selected again.

50. The same power target is used again.

51. The same gain target is used.

52. All of the weight is again assigned to the output power.

53. The best solution without any series capacitors.

54. The artwork of the solution.

55. The output power and the gain associated with the solution.

56. The next solution synthesized is similar to the first.

57. The third solution is again similar to the others.

58. The first solution will be accepted and will be exported to the circuit file.

59. The solution was exported to the circuit file.

60. The circuit with the power matching network synthesized.

61. The solution was scrolled to its end.

62. The artwork will be displayed.

63. The artwork of the amplifier with the power network in place.

64. The performance with the power network in place.

65. The Summary Table will be removed by using the command shown.

66. The Output Power Command will be selected from the Tables Menu.

67. The output power of the amplifier is listed.

68. The output power in the passband of interest.

69. The schematic will be edited to allow for biasing the drain.

70. An extra line will be added to the end of the circuit.

71. The line length can be edited by double-clicking the relevant label.

72. A series capacitor (with pads) will be inserted between the two lines.

73. An 0603 capacitor is selected.

74. The capacitor and its pads were inserted.

75. The capacitor value was changed to 22pF.

76. Parasitics are specified for the capacitor.

77. The artwork of the modified schematic will be displayed.

78. The capacitor and its pads.

79. Extra lines will be added around the capacitor to model the phase shift associated with it.

80. The first line was added.

81. The second line was added.

82. The dimensions of the new lines will be edited on the artwork.

83. The new lines are shown.

84. The Edit Dimensions Command will be used to change the lengths of the new pads.

85. The length of each pad will be set to 0.35mm (half of the gap size).

86. The second pad will be modified too.

87. Both pads are now 0.35mm long.

88. The lines are used to model the phase shift through the capacitor and should not be present physically. The line commands will be modified as required in the Text View.

89. The two “sline” commands associated with the capacitor (“sc”) will be edited.

90. The “cut : 0.35mm” commands was appended to the relevant commands.

91. The modifications made to the circuit file will be saved.

92. The Text View will be closed and a Schematic View will be opened.

93. The phase shift lines are still in place in the schematic.

94. The lengths of the two lines were reduced to zero on the artwork.

95. The effect of the added components on the performance is evaluated. The output power has not changed much.

96. The shorted stub will be replaced with a line shorted to ground at RF frequencies with a capacitor (drain biasing).

97. Topology changes must be made in a Schematic View.

98. The relevant shorted stub is selected on the schematic too. A shunt block will be inserted in parallel with this stub.

99. A line will be inserted to the right of the inductor.

100. Because the first element of the shunt block is selected the new element can be inserted to its right or to the right of the block.

101. The newly inserted line was edited to be the same as the original shorted stub (to be removed).

102. A series capacitor will be inserted to the right of the selected inductor.

103. An 0603 capacitor will be inserted.

104. The inductor will be deleted from the shunt block.

105. The inductor or the whole shunt block can be deleted.

106. A shorted stub will be inserted in parallel with the selected capacitor.

107. Extra position options are provided when the last element in a shunt block is selected.

108. The 0.1pF capacitor will be deleted.

109. The option to delete the block or the selected element is provided again.

110. DC can now be fed to the drain via the inserted shunt block. The original inductor will now be deleted.

111. The modified schematic will be saved.

112. The artwork after the modifications made.

113. Extra lines will again be inserted on both sides of the capacitor to model the phase shift effect.

114. The first line was inserted.

115. The second line was inserted.

116. The circuit should be saved often.

117. The pad lengths will be edited in the Artwork View.

118. Scrolling of the view will be turned off. This will allow centering of the view around the selected component.

119. The zoom features will be used to center the view the stub termination.

120. The lengths of the two pads will be edited.

121. The second pad will be edited too.

122. The length specified for each of the two pads.

123. The changes made will be saved.

124. The line commands will be edited in the Text View to remove the lines from the artwork.

125. The component which was selected on the artwork is also selected in the Text View.

126. Cut commands were added to the lines on each side of the capacitor.

127. The changed made will be saved.

128. The Schematic View will be opened.

129. The lines are still in place in the schematic.

130. The two lines are not shown on the artwork anymore.

131. Another shunt block will be inserted in the schematic to allow for feeding in the dc to the right of the selected line.

132. The default shunt block was inserted into the schematic. A series line will be inserted next.

133. Two position options are provided when the insert command is activated on the first element of a shunt block.

134. The series inductor will be deleted.

135. The option to delete the element or the block is provided.

136. The value of the 0.1pF capacitor will be changed to 22pF.

137. The value of the capacitor previously added must be changed too.

138. The capacitance value is changed by double-clicking the label.

139. Parasitics will be specified for the capacitors.

140. The parasitic specified for the 22pF capacitor.

141. The same parasitics are specified for the other capacitor too.

142. The performance is analyzed with the changes made. The components added did not change the output power significantly.

143. The Summary Table will be removed.

144. The length of the dc line is changed slightly to verify that the circuit performance is not sensitive to the length used.

145. The performance is checked with the modification.

146. The changes made will be saved.

147. The artwork of the circuit.

148. The gap size of the capacitor will be edited.

149. The gap size of the capacitor has been adjusted.

150. The shorted stub is selected and will be flipped to the left.

151. A bend will be introduced in the selected line.

152. A line is bent from its output side towards its input side (marked with the triangle). The line will be bent anti-clockwise.

153. The position of the bend will be changed by selecting the Bend Command again.

154. If relative position of the bend is specified as 0.65 (further away from the output side of the line).

155. The length of the output line will be increased.

156. The performance of the amplifier is analyzed again.

157. The discontinuity effect associated with the large steps in width will be reduced next.

158. The artwork options set for the circuit will be checked.

159. The option to compensate Tees/crosses is not selected. This option will be checked now.

160. All the discontinuity effects will be compensated.

161. The Analysis Options for the circuit are stored in the circuit file. The Save Command is used to save the change in these settings.

162. The dimensions of the capacitive line are viewed.

163. Lines will be inserted on both sides of the selected line in order to reduce the step transitions.

164. The line of interest is also selected on the schematic.

165. The line to the left is selected in order to insert the first new line.

166. The next line will be inserted.

167. The two lines required were inserted. The changes made will be saved.

168. The two lines will be edited on the artwork.

169. The line width will be increased to 5mm. The length should be kept short.

170. The same changes will be made to the other line too.

171. The new dimensions were specified.

172. The modified artwork is shown.

173. The performance of the modified circuit is displayed.

174. The circuit will now be optimized to restore the performance.

175. The variables to be optimized will be marked by using the command selected.

176. The variables marked for optimization are shown in blue.

177. All the lines around the capacitive line were marked for optimization.

178. The length of the shorted stub will also be optimized.

179. Optimization bounds will be set of the marked variables.

180. The bounds set for the shorted line.

181. The bounds set for the characteristic impedance of the selected line.

182. The bounds set for the characteristic impedance of the selected line

183. The bounds set for the characteristic impedance of the capacitive line

184. The bounds set for the next line.

185. The bounds set for the second 45.5 Ohm line.

186. The bounds set on the length of the selected line.

187. The bounds set on the electrical length of the next line.

188. The bounds set on the length of the capacitive line.

189. The bounds set on the length of the next line.

190. The bounds set on the length of the last line.

191. The changes made will be saved.

192. The error function for the optimization will be set up next.

193. The parameters of interest must be selected on the first page of the Error Function Wizard.

194. Only the output power and the gain will be optimized at this point.

195. The passband can be modified on this page.

196. The gain to be optimized in this case is the operating power gain.

197. The default values are derived from the performance of the network before optimization.

198. The gain values will be kept but the average gain weight factor has been set to 1.

199. The power targets must be set on this page.

200. The power weight factor was set to 1, and the minimum required power to 37.8 dBm.

201. The steps provided by the wizard have been completed.

202. The Optimization Command will be selected next.

203. The option to update the circuit with the optimized element values is provided after optimization.

204. The changes will be saved.

205. The performance after the optimization is displayed. Note that the output power has been restored.

206. The artwork of the optimized output network is displayed.

207. Last Phase of this Example The load network of the power amplifier was designed in this example. The synthesized network was extended to allow for the drain biasing of the transistor and the expected step discontinuity effects were reduced. The input network will be designed in the final phase of this power amplifier example.