1. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 ASIC Implementation of the PWA Generic Canonical Form Dpto. Electrónica y Electromagnetismo, Universidad de Sevilla Instituto de Microelectrónica de Sevilla-CNM-CSIC; acojim@imse-cnm.csic.es MOBY-DIC Project FP7-IST-248858 Noordwijkerhout, August 23, 2012 Antonio J. Acosta

2. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Introduction: Role of ASICs in control & characteristics of ASICs Design of MPC_ASICs: From high-level specifications to silicon PWAG Architecture Selection Design, Integration and test of a PWAG ASIC Test Results Outline of the presentation

3. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Model-based synthesis Description Design flow Simplification Heuristic knowledge Numerical data Verification Synthesis Tuning / Identification HW (VHDL) or SW (C, C++, Java) Non-linear plant Simulation Experiment

4. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Dedicated HW Digital ASIC Embedded Controller External memories Test board FPGA Expansion boards DSP FPGA Embedded SW - Performances + + Flexibility - - Cost +

5. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 ASIC Design Process

6. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 ASIC Design Flow

7. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 ASIC Design Example HDL Area Estimation Logical verification Timing and power estimation

8. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Moby-Dic Methodology for optimal controller

9. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Control and Circuit decisions Canonical form (PWAG) No. input-output Precision Control surface … Configurable architecture Parametrizable design Programmability issues HW requirements & limitations … MOBY-DIC TOOLBOX HDL codeParameters FOR SELECTED CASE-STUDIES

10. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Proposed PWAG Architecture MEMORY FSM Modification of the one in [OLIV09] The binary tree is stored in a Memory  The data in the TreeMemory are the address of ParamMemory  Less rigid, more configurable (different trees, on-line computation)

11. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012  Canonical Form: PWA Generic  Maximum number of inputs: 4 (configurable 1-4)  Bit number of inputs/parameters: 12-bits  Bit number of output: 26-bits (although the precision is 12)  Fixed-point arithmetic  Maximum number of polytopes plus edges: 4096  Maximum Tree depth: 13 (configurable 1-13) ASIC major specifications

12. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Technology and CAD Tools Selection Taiwan Semiconductor Manufacturing Company (TSMC)  90 nm, 9 metal layers MiniAsic:1,875 x 1,875 µm 2 (2011), 100 samples. Memories on Chip  Dual Port RAM Memories  Access and Writing times below 5 ns (worst case) CAD tools used:  DESIGN ANALYZER (SYNOPSYS)  SOC ENCOUNTER, DFWII (CADENCE)

13. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 2 14 =16384 TREE MEMORY (TMEMO) 12 TMEMO stores all the nodes of the binary tree: 2 14 -1= 2 0 + 2 1 +…+ 2 13, being 13 the maximum tree depth World lenght=12 enables 2 12 edges plus polytopes Two ck cycles for each data writing 32768 ck cycles to write the whole memory, 0.64s with a 50MHz clock Layout dimensions: 1060.95µm x 577.15µm = 612332.6µm 2 Working Modes: Writing TMEMO

14. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 2 12 =4096 PARAMETER MEMORY (PMEMO) 60 PMEMO stores all the possible edges and polytopes 2 12 = 4096 edges plus polytopes World lenght=60 enables 5 12-bit parameters Six ck cycles for each data writing 24576 ck cycles to write the whole memory, 0.48s with a 50MHz clock Layout dimensions: 1190.51µm x 569.12µm = 677543.1µm 2 Working Modes: Writing PMEMO

15. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Combinational Delay < 4ns worst case Arithmetic Unit Word length conditioning circuit for tunable fixed point Working Modes: Normal operation x1x1 h1h1 x2x2 h2h2 x4x4 h4h4 k ≤ 0 decision f(x)=f PWA (x) when a leaf is reached 24 x3x3 h3h3 26 12 26 COND.

16. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Memory Timing TMEMO TQ PORT A (write mode) PORT B (read mode) PMEMO ADDRESS PORT B (read mode) output PQ clk !clk PORT A (write mode) Output ready in only one clock cycle X1 X2X3 X4 Input Acquisition clk valid_in Fully parallel load needs 48 pins Parallel load of 12-bit inputs in 4 clock cycles If one/two/three inputs, set X2X3X4/X3X4/X4=0 Working Modes: Normal operation

17. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 PARAMETER MEMORY TREE MEMORY Arith Unit INPUT CONTROL UNIT OUTPUT Parallel load of relevant data (snapshot) Serial Test Output (shifting out the 86-bit register) Concurrent to Operation Mode Working Modes: Test test 14 12 60 clk

18. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Layout I/O Ports: 48 pins VDD/GND Ports: 12 pins Package: JLCC68 TMEMO PMEMO Area: 1860 x 1860 µm 2 Active: 1460 x 1460 µm 2 No. cells: 3135 Memory: 54 KB % Memory: 60% Post-layout simulated

19. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Structure of ASIC Operation mode P=00 Writing TMEMO mode P=01 Writing PMEMO mode P=10 Test mode P=11 No. Inputs: configurable from 1 up to 4 No. Outputs: 1 Input Resolution: 12 bits Output Resolution: 26 bits Parameters Resolution: 12 bits Maximum No. hyperplanes plus polytopes: 4096 Depth of binary search tree: configurable from 1 up to 13 Integration technology: 90nm, 2.5V-1.2V, 9 metal layers, TSMC (Taiwan Semiconductor Manufacturing Company) TMEMO: 16384x12=24KB PMEMO: 4096x60=30KB Size: 1860x1860 µm 2 Package: JLCC68

20. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Test Setup of ASIC Power supply HPE3630A Logic Analyzer Agilent 16823A Experiment controlled with Matlab Oscilloscope Agilent DSO6104A

21. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Test process of ASIC: Go/no go test Go/No go test: Simulation post-synthesis vs experimental data

22. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Test process of ASIC: Examples Double integrator, ACC and DC-DC in open-loop fashion Memory stored with parameters and trees obtained from the Moby-Dic toolbox The comparison between expected and obtained results was made by Matlab Example No. Inputs Memory contents Depth tree No. patterns TreeParameters Double Integrator21911638625 ACC4200920912625 DC-DC45722659625 Output surface (ASIC)

23. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Characterization of ASIC 20 packaged samples, allowing statistical analysis Go/no go Maximum frequency Power consumption @ DC @ 50 MHz @ fmax To discard bad samples For specific conditions AUTOMATIC FLOW

24. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Summary of results Fmax (MHz)Power @DC (mW) Power @50MHz (mW) Power @fmax (mW) ACC96.7 ± 1.71.6 ± 0.220.1 ± 0.537.0 ± 1.8 DC-DC97.5 ± 1.01.6 ± 0.222.8 ± 0.641.9 ± 1.2 Double_integrator107.51.618.138.1 100% effectiveness with very reduced variations with process Double integrator (2 inputs) reaches higher frequency and consumes less than ACC and DC-DC (4 inputs) Static power is dominated by leakage in memories

25. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Latency (ck cycles) ThroughputMultipliersMemory FPGA n+(n+2)d[Tck(n+(n+2)d)] -1 1Nr(n+1) ASIC n+2+2d[Tck(n+2d)] -1 nNr(n+1)+2 d+1 n: No. dimensions (inputs) d: depth of the tree Nr: No. Regions (edges+polytopes) Analysis of costs & performance

26. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 ACC [OLIV11] Archict. Hw resources LatencyMultipliersMemory FPGA PWAG87% occup.2.6 us13.3KB PWAS-S31% occup.390ns111.5KB PWAS-P95% occup.67 ns557.6KB ASIC PWAG3.5mm 2 120-240 ns454KB (27.3KB used) Post-layout simulation of ASIC provides 4-8 ns for clock cycle Analysis of cost&performance for CSs DC-DCArchict. Hw resources LatencyMultipliersMemory FPGA PWAG-S11% occup.3.35µs10.59KB PWAG-P10% occup.1.15µs40.59KB ASIC PWAG3.5mm 2 72-144 ns454KB (2.58KB used)

27. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 [OLIV09] A. Oliveri, T. Poggi, M. Storace, “Circuit implementation of piecewise-affine functions based on a binary search tree,” European Conference on Circuit Theory and Design (ECCTD’09), pp. 145–148, Antalya, Turkey, August 2009. [OLIV11] A. Oliveri, G.J.L. Naus, M. Storace, W.P.M.H. Heemels, "Low-complexity approximations of PWA functions: a case study on Adaptive Cruise Control“, European Conference on Circuit Theory and Design (ECCTD'11), pp. 694-697, Linköping, Sweden, August 2011. References

28. Moby-Dic Workshop, Noordwijkerhout, August 23, 2012 Conclusions and Remarks ASIC to cover different case-studies VLSI is not a simple translation from FPGA Configuration and programmability is provided -> IP hard block Extensive usage of toolbox to get surface parameters and fully functional simulation ASIC performances overtake FPGA in speed (x10) and power (÷10)