1. Front-End ASICs for CZT and Si Multi-Element Detectors Gianluigi De Geronimo Microelectronics Group, Instrumentation Division, Brookhaven National Laboratory, Upton, NY

2. Outline I.Circuit Solutions II.ASICs for CdZnTe Sensors III.ASICs for Si Sensors

3. Typical front-end channel pixel reset high-order filter baseline stabilizer to external ADC amplitude and timing extractor charge preamplifier shaper back-end processing & data concentration  high reliability  ease of use  spectroscopic quality  data concentration optimization

4. Input MOSFET optimization A3PA3P A 2 A f C g A1PA1P CgCg gmgm I p I rst CpCp CiCi IpIp Q gm,Cg,Afgm,Cg,Af P,A1,A2,A3P,A1,A2,A3 reset g m,C g,A f, are functions of input MOSFET width W and power P output IM

5. Input MOSFET optimization C g  ( C ox L+C ov )·W A f  K f / ( C ox L·W ) g m vs Pg m vs W

6. Input MOSFET optimization

8. Vdd Vgc Vgl in out current source load cascode Vgs input MOSFET g m and r o are functions of Vds Vds

9. Continuous reset of the preamplifier charge preamplifier Vgr L/W>>1, strong inversion, saturation pixel Mf Cf IpQIpQ  current gain equal to N  fully linear  self-adapts to leakage current  minimum noise contribution 1 st stage of shaper NIpNQNIpNQ N  Mf N  Cf Rs Cs CR

10. Continuous reset of the preamplifier

11. linearityoutput vs pixel leakage current

12. High order shaping A1/PA1/P 5 th cpx1 5 th 1.24 2 nd 2.64 CgCg gmgm A1PA1P

13. Output baseline stabilizer high-order shaper - + low-freq. low-pass filter x 100 + - diff. Vref BS

14. Output baseline stabilizer transfer functionperformance at high rate

15. First generation of front-end ASICs other features plug & play per-channel test capacitor programmable gain programmable peaking time high output drive capability high stability vs temperature OF

16. Generation of front-end ASICs for CZT Technology : 0.5µm CMOS SP3M CZT

17. CZT – ASIC spectra measurements 241 Am spectrum 57 Co spectrum

18. CZT – ASIC spectra measurements 241 Am spectrum 57 Co spectrum detector thickness 3mm detector bias -600V resolution 4.3% at 59keV gain 200mV/fC peaking time 1.2µs detector thickness 3mm detector bias -600V resolution 3.5% at 122keV, 21.8% at 14keV gain 200mV/fC peaking time 1.2µs

19. CZT – ASIC applications Solstice Gamma cameraeZ-SCOPE hand held Gamma camera 96 CZT crystals 3072 pixels 192 front-end ASICs 1.3M events/second average FWHM 3.8% at 122keV 1 CZT crystal 256 pixels 16 front-end ASICs 4.8M events/second average FWHM 4.0% at 122keV

20. CZT – ASIC applications Bone Densitometry – GE Lunar Detector 16 CZT crystals 16 pixels 3 x 7 x 3 mm 3 2 front-end ASICs DEXA (Dual Energy X-ray Absorptiometry) ASICs replaced 17 circuit boards (over 500 components) and improved performances

21. Highly segmented detectors Benefits: Position Resolution –pixel pitch ~ 1/  N Energy Resolution: –C DET ~ 1/N –I DARK ~ 1/N –Pulse Shaping time ~ N Rate capability –pileup ~ 1/N Benefits: Position Resolution –pixel pitch ~ 1/  N Energy Resolution: –C DET ~ 1/N –I DARK ~ 1/N –Pulse Shaping time ~ N Rate capability –pileup ~ 1/N N=1N=9N=25N=49 Drawbacks: Interconnect density –density ~ N Electronics channel count –cost ~ N –power ~ N Drawbacks: Interconnect density –density ~ N Electronics channel count –cost ~ N –power ~ N DC

22. Data concentration optimization ADCP/SDAQ Analog Memory + Analog Multiplex can be deadtimeless complex control long readout time needs trigger + multiple samples Both: slow inaccurate inefficient can’t trigger on randoms Both: slow inaccurate inefficient can’t trigger on randoms ADC P/SDAQCONCENTRATOR Track-and-Hold + Analog Multiplex unbuffered => deadtime long readout time needs accurate trigger

23. Pulse amplitude extraction : classical CMOS configurations in HOLD C h out HOLD ­ timing signal needed ­ switch charge injection ­ poor drive capability ­ deadtime until readout + power dissipation sample/hold - + in C h out reset peak-found (timing signal) +Vdd ­ accuracy impaired by op-amp offsets and CMRR ­ poor drive capability ­ deadtime until readout + self-triggered + timing signal peak detect/hold (PDH) PD

24. The two-phase PDH concept Write phase behaves like classical configuration + - in C h out v off Read phase op-amp re-used as buffer offset and CMMR errors canceled enables rail-to-rail sensing good drive capability self-switching (peak found) + - in C h out v off

25. Two-phase PDH : offset cancellation chip 1 – negative offsetchip 2 – positive offset

26. Two-phase PDH : performance Parameter: Value: PDDv1 (PDDv2) Technology0.35 um CMOS DP4M Supply voltage3.3V Input voltage range0.3 - 3.0 V Minimum peaking time500 (50) ns Absolute accuracy< 0.20% Linearity< 0.05% Droop rate250 mV/s Timing accuracy5 ns Power dissipation3.5 (2.0) mW/ch PDDv1 : absolute accuracy

27. Derandomization with N two-phase PDHs (PDD) measured derandomization ( M=16, N = 2 ) ADC N two-phase PDH output MUX M front-end channels arbitration logic & crosspoint switch PDD DD

28. Derandomization efficiency vs N The larger is N, the lower can be the fo/fi ratio

29. blocking probabilityTAC linearity Derandomization efficiency and TAC linearity

30. 32-channels PDD ASIC CROSSPOINT 32:8 INPUTS (32) COMPARATORS MUX 8:1 ARBITRATION ~5ns PD/TACs (8) t p > 50ns... channel exclude/include readout mode TAC gain TAC mode SPI INTERFACE CONFIGURATION MEMORY digital convenience outputs analog monitor powerdown FULL EMPTY ADDRESS AMPLITUDE TIME One-chip solution N CHAN = 32, N PD = 8 Dual-mode TAC –risetime –time of occurrence Amplitude, address, timing outputs 50 ns minimum pulsewidth t ARB ~ 5 ns Rate capability ~ 10 MHz SPI interface: –serial configuration of TAC gain and mode –arbitration locking –channel exclusion –powerdown –analog monitor –Digital convenience outputs (used for configuring companion amplifier chip) FIFO-like control and readout interface One-chip solution N CHAN = 32, N PD = 8 Dual-mode TAC –risetime –time of occurrence Amplitude, address, timing outputs 50 ns minimum pulsewidth t ARB ~ 5 ns Rate capability ~ 10 MHz SPI interface: –serial configuration of TAC gain and mode –arbitration locking –channel exclusion –powerdown –analog monitor –Digital convenience outputs (used for configuring companion amplifier chip) FIFO-like control and readout interface

31. 32-channels PDD ASIC : layout size : 3.2 x 3.2 mm² power : 2mW / channel technology: 0.35µm CMOS DP4M

32. Typical fluorescence EXAFS measurement geometry Sample Detector  Resolution  Rate sensor electronics  front-end  processing  readout FL

33. Resolution vs rate

34. Optimum pixellation  charge sharing (  20µm/side) and trapping (gap/side) : empirical

35. Optimum pixellation

36. quadrant (8  12=96 pixels) 96-channel front-end (3  32 channel ASICs) Peltier 20mm Si n-type high resistivity wafer 250µm thick, N = 384 p +  1mm  1mm pixels, gaps 10µm, 30µm, 50µm

37. Beam through sample sensor

38. Interconnecting pixel to front-end electronics ASIC sensor + interconnect parasitic + bond length - fringe capacitance - charge sharing and trapping + bond length - interconnect parasitic - dielectric losses ASIC sensor ASIC sensor ASIC sensor + interconnect parasitic - constraint on ASIC area and layout - fluorescence from Pb (Sn/Pb/Ag) - illumination from segmented side + dielectric losses  interconnect parasitic - bond length 6mm  10µm, Si 3 N 4 (  r =6.5,tan(  )=0.001), 3µm, C i  1.2pF IC

39. quadrant Sensor – ASIC photo

40. Front-end channel overview pixel charge preamplifier discriminators & counters low-noise reset high-order settable filter output baseline stabilizer 1 threshold 2 window 6-bit DACs for fine adjustment 24-bit SPI shaper readout  5 mW  3 mW Technology CMOS 0.35µm 3.3V 2P4M LA

41. Layouts 3  24-bit COUNTERS - 690µm 100µm 4  6-bit DACs analog - 590µm DACS digital - 170µm 5  COMPARATORS - 130µm 100µm DAC cell COUNTER cell

42. ASIC overview CMOS 0.35µm 3.3V 2P4M 180,000 MOSFETs, size 3.6  6.3 mm 2 8mW / channel 32 readout channels self adaptable continuous reset high order shaper settable peaking time (0.5µs, 1µs, 2µs, 4µs) settable gain (750mV/fC, 1500mV/fC) band-gap referenced output baseline output baseline stabilization (BLH) 1 threshold and 2 window discriminators 4  6-bit DACs for fine window adjustments 3  24-bit counters test mode analog output monitor pixel leakage current monitor Serial Peripheral Interface (SPI) global settings monitors enabling test enabling channels masking DACs setting counters readout

43. charge preamplifiershaper with BLHdiscriminators and DACscounters 32 channels, 3.6  6.3 mm 2 ASIC photo

44. Settable gain and peaking time EX

45. Correction of threshold dispersion

46. Energy resolution

47. Si – ASIC spectra measurements

50. Readout RO

51. Readout interface

52. Automatic threshold equalization before correction after correction

53. Current EXAFS detector head - preamplifiers rack – shapers …  100 channels, > 350 eV, < 1 MHz

54. New EXAFS detector  400 channels, 10MHz

55. Acknowledgment P. O’Connor Layout : A. Kandasamy Technical : J. Triolo, D. Pinelli