1. Jean-Marie Bussat – January 31, 20021 FPPA2000 characterization history Sumary of tests done at LBNL

2. Jean-Marie Bussat – January 31, 20022 First measurements Preamplifier test output Pulse input OzTek socket + Ceramic FPPA FPPA digital outputs Power supplies and temperature inputs Leakage current input FPPA output FPPA mode Selection (gains) Clock inputs  First measurements on ceramic packages started April 2001 Three problems found : Gains are wrong Preamplifier response has an undershoot Noise level is too high (40ke - )

3. Jean-Marie Bussat – January 31, 20023 Wrong gains Gains don’t have the right value: 1, 3.7, 6.4, 21 instead of 1, 5, 9, 33  Design issue: software doesn’t take care of metal resistancePreamplifier Amp. Amp. Amp.Amp. 1.3mm 0.9mm R’s R2 R1 50  External decoupling Capacitor (  100nF) Parasitic resistance ~25-30  RpRp Gain = 1 + R2 R1 + R p Small  less noise

4. Jean-Marie Bussat – January 31, 20024 Undershoot in PA response Preamp. CfCf RfRf C f = 22pF (design value) C f = 34pF

5. Jean-Marie Bussat – January 31, 20025 Excessive noise Measured Simulated Meas. Noise = 14.5Ke - + 100e - /pF Sim. Noise = 8.3Ke - + 20e - /pF "Real" noise: gaussian distribution Std. Plastic Part: Chip 2599 x25 Amplifier  =3.7 mV 0.4 pC = 270 mV  Noise = 34 ke 

6. Jean-Marie Bussat – January 31, 20026 Noise investigation (1) Noise investigation started in May 2001.  First hypothesis : process problem * Wrong size of input transistor ?  No (checked under microscope) * Intrinsic base resistor of input transistor too high ?  No (measurement of same transistor on the Process Control Monitor gives result within specs).  Second hypothesis : preamplifier not guilty, noise coming from elsewhere ? * A minimalist test setup dedicated to the preamplifier alone is built (digital part not powered, no clocks) Two attempts of re-bonding - PLCC68 - Chip on board

7. Jean-Marie Bussat – January 31, 20027 Noise investigation (2) external sources of noise Noise=pickup noise ? Noise=received “noise” ? Noise “waveform” asynchronous to 40MHz clock. Noise still there without clock. No A little : ~100-200MHz signal  Need a Faraday cage Found an aluminum box that works well L Noise still there  Comes from inside FPPA…

8. Jean-Marie Bussat – January 31, 20028 Noise investigation (3) 1st preamplifier-only test topbottom Tried with a PLCC68 package (cavity needs to be large because chip size is 4mm x 5mm) External components placed as close as possible to the chip 4cm L Package lid length: PLCC68: L ~ 1cm avg. TQFP52: L ~ 1mm (final package) Pulse shape ok with C f = 22 pF  ~ 10pF parasitics !! Need to repackage without adding parasitic capacitance  Chip on board  Too much parasitic capacitance makes preamplifier unstable

9. Jean-Marie Bussat – January 31, 20029 Noise investigation (4) 2nd preamplifier-only test topbottom Use chip-on-board direct bonding to minimize parasitic capacitances Components placed as close as possible to the chip  No more oscillations  Same noise level as with complete test board * Noise is not coming from the FPU: Preamplifier problem ??? * There’s no correlation between the noise observed on the sensitive points of the preamplifier (bias decoupling points) and the noise at the output. * It’s impossible to insure that the bias is not responsible with this setup.  Need to physically isolate the preamplifier from the FPU  "Chip surgery": FIB (Focused Ion Beam)

10. Jean-Marie Bussat – January 31, 200210 Noise investigation (5)  FIB first iteration: June 2001. * Design of a dedicated chip on board PCB * 5 chips bonded, 4 tested OK, 3 sent for FIB (preamplifier alone, no internal bias)  Noise level down to ~ 20ke - * Simulation with parasitic resistances shows an increase of noise level from 10ke - to 17ke -. Measured values are close but not enough. Ceramic FIB Schematic simulation (ideal circuit)

11. Jean-Marie Bussat – January 31, 200211 Noise investigation (6) Environmental problems Noise is studied using a spectrum analyzer instead of an oscilloscope.  Noise spectrum contains a lot of pickup noise (90-200MHz).  Noise is coupled via power supply lines Test board powered using batteries.  Noise level down to 15-17ke - : Matches simulation results

12. Jean-Marie Bussat – January 31, 200212 Noise investigation (7) Noise cause investigation: July 2001. * Previous results don’t ensure that there’s no contribution from the FPU. * The preamplifier needs a bias voltage and a bias current Simulations show that the current input is more sensitive than the voltage input  Assuming that an external bias current is the solution (like in the 1998 prototype of the FPPA that had the same noise level than in simulation), nothing proves that the contribution of the voltage input is negligible.  FIB second iteration * Standard ceramic packaged FPPA with a cut on the preamplifier bias current input only * 3 chips processed, 1 chip destroyed during transport.

13. Jean-Marie Bussat – January 31, 200213 Noise investigation (8) second FIB results ~FIB-noise2\D007~FIB-noise2\D006 4V pulse Injected 40 dB attenuation C INJ = 8 pF x25 Amplifier  =2.0 mV 0.32 pC = 255 mV  Noise = 15.7 ke  Battery powered test board Noise understood No contribution from reference voltage

14. Jean-Marie Bussat – January 31, 200214 Pulse shape study (1) Pulse shape study: July/August to October 2001. Fact: The pulse shape at the preamplifier output is affected by the setting of the FPU multiplexer. * Multiplexer set to any slow control channel  preamplifier pulse is normal. * Multiplexer set to any signal channel (gain 1, 5, 9 or 33)  preamplifier pulse is distorted.  Effect is the same for all chips (plastic or ceramic package).  Distortion is directly proportional to the value of the selected gain.  indicates a coupling through the input of the preamplifier.  Distortion looks like the derivation of the input pulse.  indicates a capacitive coupling.

15. Jean-Marie Bussat – January 31, 200215 Pulse shape study (2) Preamplifier output

16. Jean-Marie Bussat – January 31, 200216 Pulse shape study (3)  The effect has never been seen on soldered chips. - Any distortion that is visible at the output of the preamplifier is also visible at the output of the FPPA If the output of the FPPA is “clean”, the output of the preamplifier is also “clean”. - True for M0’ as well as for Proto99 and Proto99++ where no effects were observed. - Even if Proto99 and Proto99++ were using the 98’ prototype of the FPPA, some chips showed this behavior during testing (on socket). The effect was so rare that it was at that time associated to malfunctioning chips.

17. Jean-Marie Bussat – January 31, 200217 Pulse on M0' Sample number (25ns/sample) ADC count Run 11144 Max. intensity in xtal 2 (FPPA #2697) 5ns delay on ADC clock Normal pulse shape, pulse timing as simulated Pulse reconstructed from ADC data obtained with unsynchronized acquisition

18. Jean-Marie Bussat – January 31, 200218 Pulse shape (4) Pulse shape study (October 2001) :  The effect remain unchanged whatever the output buffer load is.  The preamplifier pulse is not affected by any signal applied on the slow control inputs  Pulse distortion doesn’t come from the output of the FPPA.  The effect exist if the FPU clock is running or if the FPU is forced in sample mode.  The distortion disappear if the FPU is forced in hold mode.  ????  The effect is four time smaller on FIB’d chip with external preamplifier bias.  The bias current input of the preamplifier is a coupling path.  But this is not the only one.  Pulse distortion is also visible on the IPNL test board.  The effect doesn’t come from the layout of the test board.  During three days, it was impossible to reproduce the effect whatever was done to the chip or the board.  The problem is probably coming from the contacts that are not perfects in the case of the use of a socket.

19. Jean-Marie Bussat – January 31, 200219 Pulse shape (5) Internal/External bias current Internal bias current External bias current

20. Jean-Marie Bussat – January 31, 200220 Oscillations Oscillations study: October 2001. Fact: Some oscillations have been observed at the output of the preamplifier during the test of 1500 FPPA's in Lyon.  Chips that were oscillating on the test bench in Lyon are not oscillating on the test board used at LBNL (quasi-identical layout).  The test board used in Lyon has been brought to LBNL.  No oscillations can be seen…  Environmental problem The preamplifier is sensitive to the load that is connected to its output.  It is possible, in some marginal cases, to induce an oscillation by changing the way the buffer that is used to look at the output of the preamplifier is connected.  Again, the difficulties encountered to reproduce the problem suggest that it could be related to a contact problem (No oscillations observed on the M0’ modules).

21. Jean-Marie Bussat – January 31, 200221 Timing Timing study: October 2001. Facts:* There’s some problems on the preamplifier that prevent a fine analysis of the FPU (noise and linearity measurements are dominated by the preamplifier characteristics). * Some timing problems have been observed at CERN on M0’ Timing is defined by the FPU but it is difficult to study it through the preamplifier.  FIB third iteration - Ceramic FPPA (the only type that can be modified with FIB). - The preamplifier is disconnected. Its output becomes the input of the FPPA. This way it is possible to input any given signal to the FPU to check its response. - Two fully working chips sent for modification. Both are dead after FIB : same behavior, short circuit on VCC and dead bias generator. Too sensitive node for FIB Timing has to be checked on the full FPPA (M0').