1. MICROPROCESSORS AND APPLICATIONS
SNGCE
MICROPROCESSORS AND APPLICATIONS
Mr. DEEPAK P.
Associate Professor
ECE Department
SNGCE
DEEPAK.P
DEEPAK P

2. SNGCE
UNIT 5
DEEPAK.P
DEEPAK P

3. 8086 Microprocessors
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4. Evolution of Micro Processors

5. Evolution of Micro Processors

6. 8086 Micro Processors
The 8086 ("eighty-eighty-six", also called iAPX 86) is a 16-bit microprocessor chip designed by Intel between early 1976 and mid-1978.
All internal registers, as well as internal and external data buses, were 16 bits wide.
A 20-bit external address bus gave a 1 MB physical address space (220 = 1,048,576).

7. 8086 Micro Processors
It can support up to 64K I/O ports.
It provides 14, 16-bit registers.
It has multiplexed address and data bus AD0-AD15 and A16–A19
It requires single phase clock with 33% duty cycle to provide internal timing

8. 8086 Micro Processors
It can pre-fetches up to 6 instruction bytes from memory and queues them in order to speed up instruction execution.
It is called pipelining
It requires +5V power supply.
A 40 pin dual in line package

9. 8086 Micro Processor Pipelining

10. 8086 Micro Processors It is available in three versions:
8086 (5 MHz)
(8 MHz)
(10 MHz)
It consists of 29,000 transistors.

11. Pin Diagram of 8086 Microprocessors
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12. 8086 Signals

13. Pin Diagram of 8086 Micro Processors

14. Pin Diagram of 8086 Micro Processors
8086 is a 40 pin IC.
Its operating voltage is 5 volts.
Its operating frequency is 5 MHz.
It has 16-bit data bus and 20-bit address bus.

15. Pin Diagram of 8086 Micro Processors
Address/Data Bus:
The address bus is 20 bits long and consists of signal lines A0 (LSB) through A19 (MSB).
When Address latch enable (ALE) is logic 1 it signals that a valid address is on the bus.
Status Signals:
The four most significant address lines A16 through A19 of the 8086 are multiplexed with status signals S3 through S6.

16. Pin Diagram of 8086 Micro Processors

17. Pin Diagram of 8086 Micro Processors
M/IO (memory/IO) tells external circuitry whether a memory or I/O transfer is taking place over the bus.
Logic 1 signals a memory operation and logic 0 signals an I/O operation.
DT/R (data transmit/receive) signals the direction of data transfer over the bus.
Logic 1 indicates that the bus is in the transmit mode (i.e., data are either written into memory or to an I/O device).
Logic 0 signals that the bus is in the receive mode (i.e., reading data from memory or from an input port).

18. Pin Diagram of 8086 Micro Processors
The bank high enable (BHE) signal is used as a memory enable signal for the most significant byte half of the data bus, D8 through D15.
WR (write) is switched to logic 0 to signal external devices that valid output data are on the bus.
RD (read) indicates that the MPU is performing a read of data off the bus.
During read operations, one other control signal, DEN (data enable), is also supplied.

19. Pin Diagram of 8086 Micro Processors
The READY signal can be used to insert wait states into the bus cycle so that it is extended by a number of clock periods.
Interrupt request (INTR) is an input to the 8086 that can be used by an external device to signal that it needs to be serviced.
Logic 1 at INTR represents an active interrupt request.
When the MPU recognizes an interrupt request, it indicates this fact to external circuits with logic 0 at the interrupt acknowledge (INTA) output.

20. Pin Diagram of 8086 Micro Processors
On the 0-to-1 transition of nonmaskable interrupt (NMI), control is passed to a nonmaskable interrupt service routine at completion of execution of the current instruction.
NMI is the interrupt request with highest priority and cannot be masked by software.
The RESET input is used to provide a hardware reset for the MPU.
Switching RESET to logic 0 initializes the internal registers of the MPU and initiates a reset service routine.
DMA Interface Signals:
When an external device wants to take control of the system bus, it signals this fact to the MPU by switching HOLD to the logic level 1.

21. Pin Diagram of 8086 Micro Processors
To synchronize the internal and external operations of the microprocessor a clock (CLK) input signal is used.
The CLK can be generated by the 8284 clock generator IC.
The 8086 is manufactured in three speeds: 5 MHz, 8 MHz and 10 MHz.
TEST: This input is examined by a 'WAIT' instruction.
If the TEST input goes low, execution will continue, else, the processor remains in an idle state.

22. Pin Diagram of 8086 Micro Processors
DEN-Data Enable This signal indicates the availability of valid data over the address/data lines.
8086 is designed to operate in two modes, Minimum and Maximum.
The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single microprocessor configuration.
The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi micro processors configuration

23. Architecture of 8086 Microprocessors
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24. 8086 Architecture

25. The 8086 architecture supports
16-bit ALU.
Set of 16 bit registers
Provides segmented memory addressing scheme a rich instruction set.
Powerful interrupt structure
Fetched instruction queue for overlapped fetching and execution step.
The 8086 CPU is divided into two independent functional units
Bus Interface Unit (BIU)
Execution Unit (EU)

26. 8086 Architecture Bus Interface Unit (BIU) The function of BIU is to
Fetch the instruction or data from memory.
Write the data to memory.
Write the data to the port.
Read data from the port.
Execution Unit (EU) The functions of execution unit are:
To tell BIU where to fetch the instructions or data from.
To decode the instructions.
To execute the instructions.

27. 8086 Architecture
The EU contains the control circuitry to perform various internal operations.
A decoder in EU decodes the instruction fetched memory to generate different internal or external control signals required to perform the operation.
EU has 16-bit ALU, which can perform arithmetic and logical operations on 8-bit as well as 16-bit.

28. 8086 Architecture

29. 8086 Programming Model

30. 8086 Architecture
General Purpose Registers of These registers can be used as 8-bit registers individually or can be used as 16-bit in pair to have AX, BX, CX, and DX.
AX Register: AX register is also known as accumulator register that stores operands for arithmetic operation like divided, rotate.
BX Register: This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment.
CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop counter.
DX Register: DX register is used to contain I/O port address for I/O instruction.

31. 8086 Programming Model

32. 8086 Architecture AX Register:
Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16- bit register AX.
AL in this case contains the low-order byte of the word, and AH contains the high-order byte.
BX Register:
This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment.

33. 8086 Architecture CX Register:
It is used as default counter or count register in case of string and loop instructions.
DX Register:
Data register can be used as a port number in I/O operations and implicit operand or destination in case of few instructions.
In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.

34. 8086 Architecture

35. 8086 Architecture Segment registers:
To complete 1Mbyte memory is divided into 16 logical segments.
In the complete 1Mbyte memory segmentation, Each segment contains 64Kbyte of memory.
There are four segment registers.
Code segment (CS)
It is a 16-bit register containing address of 64 KB segment with processor instructions.
The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register.
The CS register is automatically updated during far jump, far call and far return instructions.

36. 8086 Architecture Stack segment (SS)
It is a 16-bit register containing address of 64KB segment with program stack.
By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment.
SS register can be changed directly using POP instruction.
It is used for addressing stack segment of memory.
The stack segment is that segment of memory, which is used to store stack data.

37. 8086 Architecture Data segment (DS)
It is a 16-bit register containing address of 64KB segment with program data.
By default, the processor assumes that all data referenced by general
registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment.
DS register can be changed directly using POP and LDS instructions.
It points to the data segment memory where the data is resided.

38. 8086 Architecture Extra segment (ES)
It is a 16-bit register containing address of 64KB segment, usually with program data.
By default, the processor assumes that the DI register references the ES segment in string manipulation instructions.
ES register can be changed directly using POP and LES instructions.
It also refers to segment which essentially is another data segment of the memory. It also contains data.

39. Pointers and index registers.
8086 Architecture
Pointers and index registers.
The pointers contain within the particular segments.
The pointers IP, BP, SP usually contain offsets within the code, data and stack segments respectively.
Stack Pointer (SP) is a 16-bit register pointing to program stack in stack segment.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.

40. 8086 Architecture
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data addresses in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.

41. 8086 Flag Register

42. Flags Register determines the current state of the processor.
8086 Flag Register
Flags Register determines the current state of the processor.
They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program.
The 8086 flag register as shown in the fig has 9 active flags and they are divided into two categories:
1. Conditional Flags
2. Control Flags

43. 8086 Flag Register Conditional Flags Carry Flag (CY):
This flag indicates an overflow condition for unsigned integer
arithmetic.
It is also used in multiple-precision arithmetic.
Auxiliary Flag (AC):
If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry given by D3 bit to D4 is AC flag.
This is not a general-purpose flag, it is used internally by the Processor to perform Binary to BCD conversion.

44. 8086 Flag Register Parity Flag (PF): Sign Flag (SF): Control Flags
This flag is used to indicate the parity of result.
If lower order 8-bits of the result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s,the Parity flag is reset.
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.
Sign Flag (SF):
In sign magnitude format the sign of number is indicated by MSB bit.
If the result of operation is negative, sign flag is set.
Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit.

45. 8086 Flag Register Trap Flag (TF): Direction Flag (DF):
It is used for single step control.
It allows user to execute one instruction of a program at a time for debugging. When trap flag is set, program can be run in single step mode.
Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled.
It can be set by executing instruction sit and can be cleared by executing CLI instruction.
Direction Flag (DF):
It is used in string operation. If it is set, string bytes are accessed from higher memory address to lower memory address.
When it is reset, the string bytes are accessed from lower memory address to higher memory address.

46. 8086 Flag Register

47. 8086 Flag Register

48. Modes of 8086 Microprocessors
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49. 8086 is designed to operate in two modes, Minimum and Maximum.
Minimum Modes
The minimum mode is selected by applying logic 1 to the MN / MX# input pin.
This is a single microprocessor configuration.
Maximum Modes
The maximum mode is selected by applying logic 0 to the MN / MX# input pin.
This is a multi micro processors configuration

50. 8086 Modes
Minimum mode
The 8086 processor works in a single processor environment.
All control signals for memory and I/O are generated by the microprocessor.
Otherwise the 8086 itself provides all the control signals needed to implement the memory and I/O interfaces

51. 8086 Modes
Minimum mode

52. 8086 Modes

53. 8086 Modes

54. 8086 Modes
Maximum mode
Maximum mode is designed to be used when a coprocessor exists in the system.
8086 works in a multiprocessor environment.
Control signals for memory and I/O are generated by an external BUS Controller.
Otherwise separate chip (the 8288 Bus Controller) is used to help in sending control signals over the shared bus

55. 8086 Modes
Maximum mode

56. Memory Organization of 8086 Microprocessors
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57. Memory Organization
In 8086 there is 20 bit address bus,so it can address 1,048,576 address.
At each address we can store 8 bit address (1-byte)but if want to write a word(16-bit)into a memory segment to store data in byte form then we write the data in two consecutive memory address which are even(low) and odd(high) memory.
The 8086 memory address space can be viewed as a sequence of one million bytes in which any byte may contain an 8 bit data element and any two consecutive bytes may contain a 16 bit data element.

58. Memory Organization
The other bank is connected to the upper half of the data bus (D8- D15) and contains odd address bytes.
When A0 is high and BHE (Bus High Enable) is low, the odd bank is selected.
A specific byte within each bank is selected by address lines A1-A19

59. Memory Organization

60. Memory Organization
The memory address space of the 8086-based microcomputers has different logical and physical organizations
Logically, memory is implemented as a single 1M × 8 memory chunk. The byte-wide storage locations are assigned consecutive addresses over the range from through FFFFF16.
Physically, memory is implemented as two independent 512Kbyte banks: the low (even) bank and the high (odd) bank.
Data bytes associated with an even address ( , , etc.) reside in the low bank, and those with odd addresses ( , , etc.) reside in the high bank.

61. Memory Organization

62. Memory Organization

63. Segment Registers
Additional registers called segment registers generate memory address when combined with other in the microprocessor. In microprocessor, memory is divided into 4 segments as follow:

64. Segment Registers
Code Segment (CS): The CS register is used for addressing a memory location in the Code Segment of the memory, where the executable program is stored.
Data Segment (DS): The DS contains most data used by program. Data are accessed in the Data Segment by an offset address or the content of other register that holds the offset address.
Stack Segment (SS): SS defined the area of memory used for the stack.
Extra Segment (ES): ES is additional data segment that is used by some of the string to hold the destination data.

65. Even and Odd Memory Banks of 8086 Microprocessors
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66. Memory Organization
The address space is physically connected to a 16 -bit data bus by dividing the address space into two 8 bit banks of up to 512K bytes each.
One bank is connected to the lower half of the 16 bit data bus (D0- D7 ) and contains even address bytes.
When A0 bit is low, the bank is selected.

67. Memory Organization
Data can be accessed from the memory in four different ways.
They are:
8 -bit data from Lower (Even) address Bank.
8-bit data from Higher (Odd) address Bank.
16-bit data starting from Even Address.
16-bit data starting from Odd Address

68. Memory Organization

69. Memory Organization

70. Memory Organization

71. Logical and Physical address of 8086 Microprocessors
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72. 8086 Physical Memory
The total memory (1mb) of 8086 is arranged in two banks. An odd bank and an even bank. Both the banks have equal no. of locations.
The odd bank contains odd numbered memory Locations. It is known as upper bank.
The even bank contains only even numbered memory. Locations. It is known as lower bank.
This arrangement is done in order to speed up the operation

73. 8086 Physical Memory
Every memory location has two kinds of address – physical and logical.
A physical address is the 20-bit value that uniquely identifies each byte location in the Mega byte memory space.
These may range from 0 to FFFFF Hex.
All exchanges between the CPU and memory components use this physical address

74. 8086 Physical Memory
Programs deal with logical, rather than physical, addresses.
A logical address consists of a segment base value and an offset value.
For any given memory location, the segment base value locates the first byte of the containing segment and the offset value is the distance, in bytes, of the target location from the beginning of the segment.
Segment base and offset values are unsigned 16-bit quantities; the lowest-addressed byte in a segment has an offset of 0.Whenever memory is accessed, a physical address is generated from a logical address.

75. 8086 Physical Memory
This is done by shifting the segment base value four bit positions to the left (hence 16 (24) -byte boundaries) and adding the offset, as illustrated

76. 8086 Physical Memory
The logical address of an instruction always consists of a CS (code segment) and an IP (instruction pointer), shown in CS:IP format.

77. 8086 Physical Memory

78. 8086 Physical Memory

79. Interrupts in 8086 Microprocessors
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80. Interrupts

81. 8086 Interrupts

82. 8086 Interrupts

83. 8086 Interrupts

84. 8086 External Interrupts Interface Signals
Minimum Mode

85. 8086 External Interrupts Interface Signals
Maximum Mode