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Manufacturing Process
LSI Logic Japan Semiconductor Manufacturing Process
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What part at LLJS ? LSI Logic Japan Si wafer Customer Assembly
LSI Logic Japan Semiconductor LSI Logic Japan Si wafer Patterned wafer Sorted wafer Customer Assembly
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CMOS Cross Section Silicon N-Well N+ S/D P+ S/D Field Oxide P-Well
LSI Logic Japan Semiconductor CMOS Cross Section Silicon N-Well N+ S/D P+ S/D Field Oxide P-Well Poly Si Gate Gate Oxide N-MOS Tr. P-MOS Tr.
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CMOS 3LM Cross Section W Plug Meatl-3 Metal-2 Insulator Metal-1
LSI Logic Japan Semiconductor CMOS 3LM Cross Section W Plug Meatl-3 Metal-2 Insulator Metal-1 Silicon
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Cross Section of Process Flow
LSI Logic Japan Semiconductor Cross Section of Process Flow - Field Oxidation - Si3N4 SiO2 Pad P-Sub. Oxidation SiO2 Bird’s beak P-Sub.
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Cross Section of Process Flow - Implantation, Diffusion -
LSI Logic Japan Semiconductor Cross Section of Process Flow - Implantation, Diffusion - Impla Resist SiO2 P-Sub. Diff (Anneal at ~900℃） Well P-Sub.
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Process Cycle Diffusion Ion Implant Cleaning Masking CMP Etching PVD
LSI Logic Japan Semiconductor Diffusion Ion Implant Cleaning Masking CMP Etching CVD PVD
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Masking Process - Stepper Optics - Mask Elliptic Mirror
LSI Logic Japan Semiconductor Fly’s Eye Lens Mask Elliptic Mirror Mercury Arc Lamp Projection Lens Photo Resist Si Wafer
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Masking Process - Development - Exposure Developer Resist Sub. Sub.
LSI Logic Japan Semiconductor Masking Process - Development - Exposure Developer Resist Sub. Sub. Etching Sub.
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LSI Logic Japan Semiconductor
Masking Process - Projected Image -
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Cleaning Process - RCA Wet Station - HF bath OR bath SC-1 bath
LSI Logic Japan Semiconductor Cleaning Process - RCA Wet Station - DIW Filter Filter P P HF bath Oxide Strip OR bath DI water Rinse SC-1 bath Organic Remove QDR bath DI water Rinse Cooling tube DIW Filter P IPA vapor bath Drying FR bath DI water Rinse H-QDR bath Hot DI water Rinse SC-2 bath Metal Remove
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Oxidation Process - Vertical Furnace - Quartz Boat Wafer Quartz Tube
LSI Logic Japan Semiconductor Quartz Boat Wafer Quartz Tube Heater TC Exhaust Lamp Silicon chip H2, N2 O2, N2, HCl
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Ion Implatation Process
LSI Logic Japan Semiconductor Ion Implatation Process Ion Source Power Supply Analyzer Magnet Y-Scanning Plate Disk Wafer X-Scanning Plate Gas Source Slit Accelerator Ion Beam
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( Hot Wall Type Vertical Furnace )
LP-CVD Process ( Hot Wall Type Vertical Furnace ) LSI Logic Japan Semiconductor Heater Outer Tube Boat Wafer Inner Tube Quartz Cap Reactive Gas Vacuum
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(Dual Frequency, Multi-station Sequential Deposition)
LSI Logic Japan Semiconductor PE-CVD Process (Dual Frequency, Multi-station Sequential Deposition) #7 #6 #5 #4 #3 #2 #1 Reactor Chamber Loadlock
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(Wafer Face Down, Multi-D/H Sequential Deposition)
AP-CVD Process (Wafer Face Down, Multi-D/H Sequential Deposition) LSI Logic Japan Semiconductor
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- DC Magnetron Sputtering -
PVD Process - DC Magnetron Sputtering - LSI Logic Japan Semiconductor Magnet Plasma Area Target Al or Ti Ar+ Shield Ar+ Power Supply Wafer + Vacuum Pump Ar Gas
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Etching Process Process chamber GAS [ CF4, CHF3 , Cl2 ] ANODE WAFER
LSI Logic Japan Semiconductor Process chamber GAS [ CF4, CHF3 , Cl2 ] ANODE WAFER CATHODE RF POWER VACUUM PUMP
![Etching Process Process chamber GAS [ CF4, CHF3 , Cl2 ] ANODE WAFER](http://slideplayer.com./slide/7431838/24/images/18/Etching+Process+Process+chamber+GAS+%5B+CF4%2C+CHF3+%2C+Cl2+%5D+ANODE+WAFER.jpg "LSI Logic Japan Semiconductor. Process chamber. GAS [ CF4, CHF3 , Cl2 ] ANODE. WAFER. CATHODE. RF POWER. VACUUM PUMP.")
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CMP (Chemical Mechanical Polishing)
LSI Logic Japan Semiconductor CMP (Chemical Mechanical Polishing) Process Principle Slurry Force Wafer Carrier Polishing Pad Wafer Table The surface of the wafer is polished by the slurry.
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In-Line Monitoring Tools
LSI Logic Japan Semiconductor
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In-Line Monitoring Flow 1 Defect Classification
LSI Logic Japan Semiconductor Defect Map Trend Chart Wafer Inspection Microscope SEM Defect Classification
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In-Line Monitoring Flow 2
LSI Logic Japan Semiconductor Elemental Analysis (EDX) Analysis & Investigation Cross-Section (FIB) Feedback to Root Cause Electron Mode Ion Mode
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Process Trend Lithography : KrF, ArF, F2, EUV
LSI Logic Japan Semiconductor Lithography : KrF, ArF, F2, EUV Metallization : Cu, Low-K Manufacturing : 300mm, Single Wafer
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Semiconductor Business
LSI Logic Japan Semiconductor Semiconductor Business 226.5 B$ ~ World / yr 2000 B$ ~ LSI / yr 2000
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