1. Group M1 Insik Yoon Mehul Jain Umang Shah SritejaTangeda Team Manager Prajna Shetty Secure unique Smart Card Reader Wednesday 2 nd December, 2009

2. Outline Motivation for the Smart Card with applications Potential for the Card What is SecurOne? Applications Market Potential Project description Basic Functional blocks Behavioral description Design Process Floorplans Layout Verification Conclusion

3. Motivation for the Smart Card Smart Card: – identification, authentication, and data storage. – a means of effecting business transactions. – strong authentication for multiple application access. Potential competitors: – Karta Miejska (Warsaw, Poland) – Navigo card(Paris, France) – YTV travel card (Helsinki, Finland), etc. Greater security demand!

4. Smart Card Applications Identification – Passport details, driver’s license information, school ID. Billing – Any Credit & debit card applications. Ticketing information – Bus / Train rides. – Tourists Attractions and Sporting Events. – Discount in groceries / department stores. RFID tag reader – Highway pass detection.

5. Market potential for such a card Huge target market : – If used as a national ID, there are 217.8 million people above the age of 18 in the United States alone. – Ease of transaction to 181 million people (by 2010) with credit cards in the United States only. India is trying to introduce a Unique ID for all its citizens. This can be targeted as a potential starting point for this product. – Potential billion customers.

6. However…. We need Hardware to access / modify information on the card. This calls for a Reader which can do the above functions in a secure way. Goal Make a smart card reader which has an encryptor and a decryptor along with a fingerprint matching feature to access / modify data on card.

7. What is SecurOne? A card reader for a potential Universal Smart Card which stores information such as ID, credit information and others. Key features: More secured way of accessing critical information (finger print matching along with encryption). Details can be modified through the internet and updated through an easily accessible card reader. A unified approach for all these requirements while ensuring proper security.

8. Applications Read / update information on the card for – Bus / Train rides. – Tourists Attractions and Sporting Events. – Discount in groceries / department stores. Encrypt/Decrypt the card information Fingerprint matching with the user.

9. Market Potential Will handle a lot of sensitive information. – Security is a major issue. – And we provide it through encrypted information and finger print matching. User can update information stored on the card – The card readers currently present in the market can only read the data stored on a card. – SecurOne enables active interaction between card and a user.

10. Outline Motivation for the Smart Card with applications Potential for the Card What is SecurOne? Applications Market Potential Project description Basic Functional blocks Behavioral description Design Process Floorplans Layout Verification Conclusion

11. Project description SecurOne Smart Card Reader Obtain and compare the finger print data from the card and the user. Perform the following functions in a secured method: – Update – Display – Transaction

12. Top View-SecurOne

13. Basic Functional Blocks Encryption/Decryption Block –16-bit TEA Encryption and Decryption Comparator –16-bit Comparator FSM for Operations –Main FSM –Init FSM –Update FSM –Transaction FSM –Display FSM SRAM for all the data storage –32-bit, 16-bit and 5-bit SRAMs

14. Encryption and Decryption Used TEA(Tiny Encryption Algorithm) encryption algorithm for encrypting the data to be stored on the card. The encryption and decryption was performed using 10 computation cycles. Data Required: –Plain text (encryptor) : 16 bits –Key : 32 bit (4 sub-keys each 8 bits long) –Delta : 16 bit magic number Algorithm: V 0 + = ((V 1 >5)+k 1 ) V 1 + = ((V 0 >5)+k 3 )

15. Control Unit Initial Initial FSM Flow Chart Card Reader Finger Print Reader Decryptor SRAM 4 BYTE Finger Print Data Co mp A B B 1 1 1 1 1 1 1 16 G C C C D E E F F F 1  External Blocks  Computational and Memory Blocks  FSM Blocks

16. Control Unit Initial Main Menu FSM Display Unit User Control Unit Update Control Unit Display Control Unit Trans. 1 A B 1 C 2 C={00} Control Unit Exit Init  Main  Update

17. Update FSM Flow Chart Control Unit Update SRAM 5Bit (Choice Regfile) Display Unit User Encryptor Central Server Interface SRAM 4 BYTE Finger Print Data Smart Card 1 1 5 16 5 1 11 A B C D E F G H H I 1 J Main Menu FSM C D 1 E 1 1 H 5 H

18. Display Unit User Control Unit Update Control Unit Display Control Unit Trans. B 1 C 2 C={01} Control Unit Exit Main  Display

19. Display FSM Flow Chart Control Unit Display SRAM 5Bit (Choice Regfile) Display Unit User Decryptor SRAM 2 BYTE Display Data Smart Card Main Menu FSM A 1 B 1 C 5 C 1 D 1 5 E F 16 F 1 G 1 H H 1 I 1 I 1 J K 1 E 1

20. Main Menu FSM Display Unit User Control Unit Update Control Unit Display Control Unit Trans. B 1 C 2 C={10} Control Unit Exit Main  Transaction

21. Transaction FSM Flow Chart Control Unit Trans. SRAM 5Bit (Choice Regfile) Display Unit User Decryptor SRAM 2 BYTE Transaction Data Smart Card Main Menu FSM A 1 B 1 CC 5 1 D 1 E5 F 1 F 16 G 1 H H 1 Display Unit Vendor I 1 I 16 J 1 K 1 E 1

22. Main Menu FSM Display Unit User Control Unit Update Control Unit Display Control Unit Trans. B 1 C 2 C={11} Control Unit Exit Control Unit Initial Exit

23. Outline Motivation for the Smart Card with applications Potential for the Card What is SecurOne? Applications Market Potential Project description Basic Functional blocks Behavioral description Design Process Floorplan Layout Verification Conclusion

24. Design Process Verilog –Behavioral –Structural –Testing Schematic Simulation Layout

25. Verilog Behavioral Verilog modeling – To test the logical functionality of the blocks, each logical block was first designed in behavioral verilog and run through several testing cycles. Final Structural Verilog version – In order to facilitate the transition to schematic, a structural version of the same was modeled and went through several iterations of modifications and testing.

26. Schematics Transmission Gate Logic was avoided to have an electrically safe circuit. In order to cater for the extremely regular layout design, a careful choice of transistor sizes was required (so as to minimize the number of different transistor sizes). The following transistor finger size was used: PMOSNMOS 750n300n

27. Layouts The entire layout was done following the rules of Extremely Regular Layout. Each transistor was custom laid and the number of different transistor sizes was minimized. Poly Extension on Active was increased to improve printability. Double contacts were used on poly to provide redundancy. Used a Poly Pitch = Metal1 Pitch = Metal3 Pitch = 0.42um. Used a fixed Metal2 and Metal 4 pitch of 0.5um for the entire chip.

28. Encryptor Decryptor 4 B SRAM Comparator Choice Regfile Display SRAM 2B Trans. SRAM 2B Update FSM Display FSM Trans. FSM Initial FSMExit Main Menu FSM FLOOR-PLAN 1

29. Main Menu 170 x 6 Routing Channels Project Evolution: Floor-plan 2 16 bit SRAM Display 2.4 x 88 16 bit SRAM Trans- action 2.4 x 88 16 bit SRAM FP 1 2.4 x 88 16 bit SRAM FP 2 2.4 x 88 Encryptor 170 x 88 Decryptor 170 x 88 16 bit Comparator 14 x 88 5 bit choice Update 2.4 x 18 5 bit choice Display 2.4 x 18 5 bit choice Trans 2.4 x 18 Update FSM 42 x 44 Display FSM 42 x 44 Transaction FSM 42 x 44 Init FSM 42 x 44

30. Encryptor 170 x 88 Decryptor 170 x 88 Main Menu FSM 42x 10 Routing Channels 16 bit SRAM Display 2.4 x 88 16 bit SRAM Trans- action 2.4 x 88 16 bit SRAM FP 1 2.4 x 88 16 bit SRAM FP 2 2.4 x 88 16 bit Comparator 14 x 88 5 bit choice Update 2.4 x 18 5 bit choice Display 2.4 x 18 5 bit choice Trans 2.4 x 18 Update FSM 42 x 44 Display FSM 42 x 44 Transaction FSM 42 x 35 Init FSM 42 x 35 Routing Channels Project Evolution: Final Floor-plan

31. Final Layout – Chip Layout Decryptor Encryptor Display FSM Transactio n FSM Main FSM Update FSM Initial FSM 16 bit Reg-files 5 bit Reg- file HLFF bank

32. Layout of Display FSM

33. Layout of Transact FSM

34. Layout of Main FSM

35. Layout of Update FSM

36. Layout of Init FSM

37. Outline Motivation for the Smart Card with applications Potential for the Card What is SecurOne? Applications Market Potential Project description Basic Functional blocks Behavioral description Design Process Floorplan Layout Verification Conclusion

38. Verification Done at 2 different levels – Functional Behavioral Verilog Structural Verilog – Schematic The individual blocks were tested at the schematic level before integrating them. Several vector tests were conducted on each block separately. The entire module was then integrated and tested with 5 different vector inputs. The module was tested with a 2 ns clock.

39. Verification 0 0 1 0 1

40. 0 0 0 1 2

41. 0 0 1 1 3

42. 0 1 0 0 4

43. 1 1 1 1 F

44. 1 1 1 0 D

45. 0 1 1 0 5

46. 1 0 0 0 8

47. Card insert signal goes high, indicating the card is inserted. The finger print data from the card is compared with the one from the reader and if a match occurs, Comparator_complete goes high. 2ns global clock Wordline goes high to store the FP data from the reader. User makes Main Menu choice. Update_ON indicates the control is transferred from the Main FSM to update. Main Menu Choice 00

48. Verification Display_Update signal goes high to indicate the update menu being displayed. Indicates the choice of submenu the user wants to update. Once the choice is set, the choice_ready signal goes high. Wordline of the choice reg file goes high, to store the value of the field that needs to be updated. Once the Info arrives from the central server, the control is transferred to the Encryptor. CS_Control signal indicates that the info has been sent by the Central server.

49. Verification This signal is used to assert the Write-Enable of the Smart Card. Update choice sent to the Smart Card. Reset_update goes high. Indicating the end of Encryption. Update_complete is asserted to transfer control back to the main FSM.

50. Final Layout – Chip Layout DeltaKey Data Into Encryptor Encrypted Data Data Into Decryptor Decrypted Data Data from FP Reader Input into Choice Regfiles

51. Specifications Area =94539.1536µm 2 – 502.12um x 188.28um – 1:2.66 Aspect Ratio Transistors : 17236 Density – 0.18231 transistors / µm 2 I/O’s – 114 inputs – 49 outputs BlockTransistor Count Encryption/Decryption 13000 FSMs (Including SRAMS) 3616 Comparator 620

52. Conclusion Implemented smart card reader. Main components : SRAM, FSMs, TEA encryptor/decryptor. Used Verilog and Cadence Spectre simulation for verification. Adapted extremely regular layout techniques.

53. SecurOne System Flip it around to insert the card Finger print scanner. Power on and power off buttons. Display Update Transact Exit Touch screen Display

54. Thank You