1. Section II Basic PLD Architecture

2. Section II Agenda  Basic PLD Architecture —XC9500 and XC4000 Hardware Architectures —Foundation and Alliance Series Software

3. Section II Basic PLD Architecture XC9500 and XC4000 Hardware Architectures

4. XC9500 CPLDs  5 volt in-system programmable (ISP) CPLDs  5 ns pin-to-pin  36 to 288 macrocells (6400 gates)  Industry’s best pin- locking architecture  10,000 program/erase cycles  Complete IEEE 1149.1 JTAG capability Function Block 1 JTAG Controller Function Block 2 I/O Function Block 4 3 Global Tri-States 2 or 4 Function Block 3 I/O In-System Programming Controller FastCONNECT Switch Matrix JTAG Port 3 I/O Global Set/Reset Global Clocks I/O Blocks 1

5. XC9500 - Architectural Features  Uniform, all pins fast, PAL-like architecture  FastCONNECT switch matrix provides 100% routing with 100% utilization  Flexible function block —36 inputs with 18 outputs —Expandable to 90 product terms per macrocell —Product term and global three-state enables —Product term and global clocks —Product term and global set/reset signals  3.3V/5V I/O operation  Complete IEEE 1149.1 JTAG interface

6. XC9500 Function Block To FastCONNECT From FastCONNECT 2 or 4 3 Global Tri-State Global Clocks I/O 36 Product- Term Allocator Macrocell 1 AND Array Macrocell 18 Each function block is like a 36V18 !

7. XC9500 Product Family 9536 Macrocells Usable Gates t PD (ns) Registers Max I/O 3672108144216 8001600240032004800 57.5 10 3672108144216 3472108133166 Packages VQ44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ160 288 6400 10 288 192 HQ208 BG352 PQ160 HQ208 BG352 957295108951449521695288

8. XC9500XL 3.3V Key Features  High performance —t PD = 4ns, f SYS = 200MHz  36 to 288 macrocell densities  Lowest price, best value CPLD  Highest programming reliability —10,000 program/erase cycles  Most complete IEEE 1149.1 JTAG support  Space-efficient packaging, including chip scale pkg  Industry’s first 0.35um Flash CPLD XC9500 XC9500XL 125MHz 200MHz

9. XC9500XL Embraces In- System Changes  Identical FBs, macrocells and I/Os  Maximum Flexibility —54-input function block fan-in —90 p-terms per output —3 global, locally invertible clocks —global set/reset pin —p-term OE per macrocell —clock enable  Advanced, 2nd Generation Pin-Locking

10. New XC9500XL 3.3V Family XC9536XL Macrocells Usable Gates t PD (ns) f SYSTEM 3672 8001600 45 200178 Packages (Max. User I/Os) 44PC (34) 64VQ (36) 48CS (36) 44PC (34) 64VQ(52) 100TQ (72) 48CS (38) XC9572XL 144 3200 5 178 100TQ (81) 144TQ (117) 144CS (117) XC95144XL 288 6400 6 151 144TQ (117) 208PQ (168) 352BG (192) XC95288XL CSP BGA

11. XC4000 Architecture Programmable Interconnect I/O Blocks (IOBs) Configurable Logic Blocks (CLBs)

12. XC4000E/X Configurable Logic Blocks  2 Four-input function generators (Look Up Tables) - 16x1 RAM or Logic function  2 Registers - Each can be configured as Flip Flop or Latch - Independent clock polarity - Synchronous and asynchronous Set/Reset

13. Look Up Tables  Capacity is limited by number of inputs, not complexity  Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM  Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB  Example: A B C D Z 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1... 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 Look Up Table Combinatorial Logic A B C D Z 4-bit address G Func. Gen. G4 G3 G2 G1 WE 2 (2 ) 4 = 64K !

14. XC4000X I/O Block Diagram Shaded areas are not included in XC4000E family.

15. Xilinx FPGA Routing  1) Fast Direct Interconnect - CLB to CLB  2) General Purpose Interconnect - Uses switch matrix CLB Switch Matrix Switch Matrix  3) Long Lines —Segmented across chip —Global clocks, lowest skew —2 Tri-states per CLB for busses  Other routing types in CPLDs

16. Other FPGA Resources  Tri-state buffers for busses (BUFT’s)  Global clock & high speed buffers (BUFG’s)  Wide Decoders (DECODEx)  Internal Oscillator (OSC4)  Global Reset to all Flip-Flops, Latches (STARTUP)  CLB special resources — Fast Carry logic built into CLBs — Synchronous Dual Port RAM — Boundary Scan

17. What’s Really In that Chip? CLB (Red) Switch Matrix Long Lines (Purple) Direct Interconnect (Green) Routed Wires (Blue) Programmable Interconnect Points, PIPs (White)

18. XC4000XL Family * 25-30% of CLBs as RAM * 20-25% of CLBs as RAM 4005XL4010XL4013XL4020XL4028XL Logic Cells4669501,3681,8622,432 Typ Gate Range* 3 - 9K7-20K10-30K13-40K18-50K (Logic + Select-RAM) Max. RAM bits6K13K18K25K33K (no Logic) I/O112160192224256 Initial PackagesPC84PC84PQ100 PQ160PQ160PQ160PQ160 PQ208PQ208PQ208PQ208HQ208 PQ240PQ240HQ240 BG256BG256BG256BG352 4036XL4044XL4052XL4062XL4085XL 40125XV Logic Cells 3,078 3,8004,5985,4727,44810,982 Typ Gate Range* 22-65K 27-80K33-100K40-130K55-180K78-250K (Logic + Select-RAM) Max. RAM bits 42K 51K62K74K100K158K (no Logic) I/O 288 320352384448544 Initial packages HQ208 HQ240 HQ240HQ240HQ240 BG352 BG432BG432BG432BG432 PG411PG411PG411PG475PG559PG559 BG560BG560BG560BG560

19. CPLD or FPGA?  CPLD  Non-volatile  JTAG Testing  Wide fan-in  Fast counters, state machines  Combinational Logic  Small student projects, lower level courses  Control Logic  FPGA  SRAM reconfiguration  Excellent for computer architecture, DSP, registered designs  ASIC like design flow  Great for first year to graduate work  More common in schools  PROM required for non- volatile operation