1. SLAAC SV2 Briefing SLAAC Retreat, May 2001 Heber, UT Brian Schott USC Information Sciences Institute

2. SLAAC-1V Architecture Review 64/66 PCI X0 X1X2 CC Three Virtex 1000. 3M logic gates @ 200MHz. Use Xilinx 64/66 core. Virtex100 configuration controller, FLASH, + SRAM. Ten 256Kx36 ZBT SRAMs. Bus switches allow single- cycle memory bank exchange between X0 and X1/X2. Three I/O connectors. Three port crossbar gives access to other FPGAs or local external I/O connector. User Interface IF X0 72 XXX 60 S F

3. SLAAC-1V Lessons Learned Integrating PCI core with user design is still not practical with commercial tools. Tools don’t merge placed and routed designs. Memory exchange switches are useful, but pay a real price in memory performance. Custom I/O interface boards are difficult to build and program. Memory mezzanine cards save real-estate, but add cost and complexity. Onboard SDRAM storage would be useful.

4. SV2 Block Diagram IF is Virtex-II 1000 FPGA with (2) 64/66 PCI. XP is Virtex-II 6000 (6M Gates, 824 User IO). (10) 512Kx36 200MHz ZBT SRAM. (2) 144-pin SODIMM (512MB PC133 SDRAM). (2) 32-pin LVTTL or (2) 16-pair LVDS busses. PMC I/O connector with 64/66 PCI. IF XC2V1000 SODIMM XP XC2V6000 64/66 PCI 64/66 PMC

5. SV2 Placement (Front) Configuration SRAM (6) IF FPGA Virtex-II 1000 (4) PMC Connectors XP FPGA Virtex- II 6000 (2) S0DIMM Connectors (7) 512Kx36 ZBT SRAM

6. SV2 Placement (Back) (3) 512Kx36 ZBT SRAM

7. 144 Pin SODIMM Low profile laptop DIMMS, PC100 or PC133. http://images.micron.com/pdf/datasheets/modules/ZM46.pdf

8. PMC Connector Set PMC stands for PCI Mezzanine Card. A set of 2 to 4 connectors used for I/O cards for VME and Compact PCI single board computers. Connectors 1&2 implement 32/33 PCI. Connector 3 adds 64-bit PCI. Connector 4 is general purpose I/O. Processor PMC specification is a Motorola draft standard that allows 64/66 PCI and PCI bus mastering from mezzanine card side.

9. Example Processor PMC See the draft at: http://www.mcg.mot.com

10. Schedule Virtex-II 6000 available July 1. First batch hardware completed August 1. Base firmware October 1. Production run in November.

11. Discussion Topics 64/66 PCI only! Internal memory ring. JHDL Support. Dual-PCI bridge. Name!

12. GRIP Packet Engine Network Security Challenge Breakout Meeting

13. GRIP Network Bridge 64/66 PCI X0 X1X2 Standardize X0 design for optimized packet data movement. Standard GbE interface. Dump packets in SRAMs. Common hardware assist (checksum, etc.). Custom packet processing in X1/X2. GRIP encrypt/decrypt. NFR Rules processing. X0 GRIP Packet Engine 72 60 GRIP GbE

14. GRIP X0 Detail DMA Packet Mover PCI (32/33,64/66) XMAC TX,RX,CTRL 72 pins to X272 pins to X1 GRIP board 60 pins to X2 memories60 pins to X1 memories