1. AT91 Embedded Peripherals
This training module provides an overview of the advanced peripheral functions available on some MCUs in the AT91 series. It’s important to emphasis the fact that ATMEL is not just another ARM based microcontroller supplier. The core is one thing but the richness and complexity of associated peripheral will make whole architecture a real solution for embedded applications.

2. SYSTEM and USER PERIPHERALS Overview
System Peripherals
External Bus Interface
Advanced Interrupt Controller
Parallel I/O Controller
Watchdog
Peripheral Data Controller
System Timer
Power Management Controller
Real Time Clock
User Peripherals
USART
Serial Peripheral Interface
Timer Counter
Analog to Digital Converter
Digital to Analog Converter
The AT91 microcontrollers integrate several peripherals, which are classified as system or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA bridge and can be programmed with a minimum number of instructions. The peripheral register set is composed of control, mode, data, status and enable/disable/status registers.

3. PIO Controller : Features
Up to 32 Programmable Input Output lines
I/O lines may be multiplexed with an on-chip peripheral signal to optimize the use of available package pins managed by the PIO controller
Input Change Detection Interrupt on each line
Available even in Peripheral mode
Multi Driver (Open-Drain)
Allows multiple devices to drive the PIO lines
Reset state : all PIO configured as PIO in input
PIO Multiplexed with EBI signals do not respect this rule
Depending on the device, the AT91 microcontroller can have up to 2 PIO Controllers. The PIO Controller has 32 programmable IO lines, with pins dedicated as general purpose I/O pins and the other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins.
The PIO Controller enables the generation of an interrupt on input change on any of the PIO pins. After Reset, the pin is controlled by the PIO Controller and is in input.
Each IO can be programmed for multi-driver option. This means that the I/O is configured as open drain in order to support external drivers on the same pin. An external pull-up is necessary to guarantee a logic level of one when the pin is not being driven.

4. PIO Controller : Block Diagram

5. PIO Controller : I/O Levels
Each pin can be configured to be driven high or low
The level is defined in four different ways, according to the following conditions :
If a pin is controlled by the PIO Controller and is not defined as an output, the level is determined by the external circuit.
If a pin is controlled by the PIO Controller and is defined as an output, the level is programmed using the registers Set Output Data (PIO_SODR) and Clear Output Data (PIO_CODR).
If a pin is not controlled by the PIO Controller, the state of the pin is defined by the peripheral.
In all cases, the level on the pin can be read in the register PIO_PDSR (Pin Data Status).

6. AIC : Features 8-level Priority Up to 32 Interrupt sources
Individually maskable
Hardware interrupt vectoring
Internal Interrupt sources
Level sensitive or edge triggered
External Interrupt sources
Low/High level sensitive or positive/negative edge triggered
The AT91 microcontroller embeds an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real time overhead in handling internal and external interrupts. Internal sources are programmed to be level sensitive or edge triggered. External sources can be programmed to be positive or negative edge triggered or high or low level sensitive.

7. AIC : Block Diagram

8. WD : Features 16-bit Down Counter Programmable Time-out Period
4ms to 8s, with 33MHz system clock
4 Clock sources
MCK/32, MCK/128, MCK/1024 and MCK/4096
3 Independent Outputs
Internal Reset
Internal Interrupt
Low level on Watchdog overflow signal for a duration of 8 MCK cycles
Control access keys
The watchdog timer has a 16-bit down counter. Four clock sources are available to the watchdog counter and provides a programmable time-out period of 4ms to 8s with a 33MHz system clock. If an overflow occurs, the watchdog can generate an internal reset, internal interrupt or a low level on the NWDOF signal. All write accesses are protected by control access keys to help prevent corruption of the watchdog.

9. WD : Block Diagram

10. WD : Software Checking
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. In normal operation the user reloads the watchdog at regular intervals before the timer overflow occurs. If an overflow does occur, the watchdog timer generates one or a combination of signals.

11. ST : Features One Period Interval Timer (PIT) One Watchdog Timer (WD)
16-bit programmable counter
periodic interrupt, useful for OS
One Watchdog Timer (WD)
maximum watchdog period of 256s with a typical slow clock of kHz
One Real Time Timer (RTT)
20-bit free-running counter
count elapsed seconds
1s increment with a typical slow clock of kHz
count up to s (12 days)
Alarm to generate an interrupt
The System Timer module integrates three different free-running timer: A Period Interval Timer which provides periodic interrupts for use by operating system. It is build around a 16-bit down counter.
A Watchdog timer which can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is buils around a 16-bit down counter. It uses the slow clock divided by 128, this allows the maximum watchdog period to be 256s with a typical slow clock of kHz.
A Real Time Timer, which can be used to count elapsed seconds. It is build around a 20-bit counter. The 20-bit counter can count up to s, corresponding to more than 12 days.

12. ST : Block Diagram

13. TC : Features Three 16-bit Timer/Counter channels
Wide range of functions:
Frequency measurement
Event counting
Interval measurement
Pulse generation
Delay timing
Pulse Width Modulation
Clock inputs
3 External and 5 Internal
Two configurable Input/Ouput signals
Internal interrupt signal
Depending on the device, the AT91 microcontroller can have up to 2 Timer/Counter Blocks. Each containing three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
Each Timer Counter channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts via the AIC.

14. TC : Block Diagram

15. TC : Clock Selection
Internal clock signals: MCK/2, MCK/8, MCK/32, MCK/128, MCK/1024
External clock signals: XC0, XC1, XC2
Selected clock can be inverted
Burst Function
Each channel can independently select an internal or external clock source for its counter: Internal clock signals: MCK/2, MCK/8, MCK/32, MCK/128 and MCK/1024, External clock signals: XC0, XC1 and XC2. The selected clock can be inverted to allow counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high.

16. TC : Clock Control
Counter clock can be enabled/disabled and started/stopped
Software Enabling Commands by Control Register : CLKEN and CLKDIS
Loading RB in Capture Mode or RC Compare in Waveform Mode can stop or disable the counter clock
The clock of each counter can be controlled in two different ways, it can be enabled/disabled and started/stopped.

17. TC : Operating Modes Two different modes:
Capture Mode allows measurement on signals,
Waveform Mode allows wave generation.
Timer Counter Mode programmed with the WAVE bit in the TC Mode Register.
Each Timer Counter channel can independently operate in two different modes: Capture Mode allows measurement on signals Waveform Mode allows wave generation.

18. TC : Triggers
A trigger resets the counter and starts the counter clock.
The following triggers are common to both modes:
Software Trigger
Each channel has a software trigger, available by setting SWTRG in TC_CCR.
SYNC
Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.
Compare RC Trigger
RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR.
External triggers:
TIOA or TIOB in Capture Mode
TIOB, XC0,XCC1 or XC2 in Waveform Mode

19. TC : Capture Mode (1/3) TIOB input TIOA input Capture Register A
Selected
Clock
Capture
Register A
Capture
Register B
Register C
16-bit Counter
RC Compare
SYNC
SWTRG
CPCTRG
LDRA
LDRB
ABETRG
TIOB
input RA
Loading
Logic RB
Loading
Logic
Edge
Detector
Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as input. Registers A and register B are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on signals TIOA and TIOB.
ETRGEDG
TIOA
input
TIOA and TIOB as input pins
RA Loading Logic : can be loaded only after a trigger or if RB has been loaded
RB Loading Logic : can be loaded only after a trigger and if RA has been loaded

20. TC : Capture Mode (2/3) Examples:
Measure the phase between TIOB and TIOA and the duration of the TIOA pulse
TIOB rising edge resets and starts the counter
TIOA rising edge loads RA and a falling edge loads RB
RA contains the phase between TIOB and TIOA
(RB-RA) is the duration of the TIOA pulse

21. TC : Capture Mode (3/3) Measure the duration of a TIOA pulse or period
TIOA falling edge resets and starts the counter and loads RB if RA is already loaded
TIOA rising edge loads RA
RA contains the duration of a TIOA pulse (low level)
RB contains the duration of the TIOA period

22. TC : Waveform Mode (1/2) TIOA output TIOB output TIOB input Register A
Register B
Register C
Selected
Clock
16-bit Counter
RA Compare
RB Compare
RC Compare
ASWTRG
SYNC
AEEVT
TIOA
output
SWTRG
CPCTRG
ACPC
ACPA
ENETRG
EEVT
BSWTRG
XC0
Edge
Detector
BEEVT
TIOB
output
XC1
XC2
BCPC
EEVTEDG
BCPB
Waveform Mode allows the TC channel to generate 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or to generate different types of one-shot or repetitive pulses. In this mode, TIOA is configured as ouput and TIOB is defined as ouput if it is not used as an external event. RA, RB and RC are all used as compare registers.
TIOB
input
TIOA is an output
TIOB can be input or output depending on EEVT programming ( default is input )
Output controllers can set, clear or toggle outputs in function of events

23. TC : Waveform Mode (2/2) Examples:
Dual Pulse Width Modulation (PWM) generation
TIOA is toggled by RA and RC, TIOB by RB and RC
A trigger starts the counter and initializes TIOA and TIOB
The PWM frequency must be stored in the compare register RC
The duty cycles on TIOA and TIOB are defined by RA and RB respectively

24. USART : Features
Programmable Baud Rate Generator with External or Internal Clock
Up to 1Mbits/s in Asynchronous Mode and up to 16Mbits/s in Synchronous Mode at 32MHz
Parity, Framing and Overrun Error Detection
Line Break generation and detection
Automatic Echo, Local Loopback and Loopback Channel Modes
Multi Drop Mode : Address Detection and Generation
Interrupt Generation
2 Dedicated PDC Channels
5,6,7,8 and 9-bit Character Length
Transmitter Time Guard
Depending on the device, the AT91 microcontroller can have up to three identical, full duplex, universal synchronous/asynchronous receiver/transmitters which are connected to the Peripheral Data Controller.

25. USART : Block Diagram

26. USART : Baud Rate Generator
Asynchronous Mode
Baud rate = MCK period / 16 / CD
Synchronous Mode
Baud Rate = MCK period / CD
The Baud Rate Generator provides the bit period clock (the Baud Rate clock) to both the receiver and the transmitter. The Baud Rate Generator can select between external and internal clock sources. The external clock source is SCK and the internal clock sources can be either the master clock MCK or the master clock divided by 8 (MCK/8).

27. USART : Reception Asynchronous: 8 bit 1 start and 1 stop
In Asynchronous mode, the USART detects the start of a received character by sampling the RXD signal until it detects a valid start bit. when a valid start bit has been detected, the receiver samples the RXD at the theorical mid-point of each bit. In Synchronous Mode, the receiver samples the RXD signal on each rising edge of the baud rate clock.

28. USART : Transmission
Asynchronous and Synchronous : 8 bit, parity and 1 stop
The transmitter has the same behavior in both synchronous and asynchronous operating modes. Start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first, on the falling edge of the serial clock.

29. USART : PDC Channels PDC shares the ASB bus with the ARM Core
External or Internal Memories Access
ARM Core stopped during 3 cycles min.
Each PDC channel is dedicated to a peripheral and a transfer direction
PDC Registers mapped in User Interface
End of Transfer in the Status Register
Typical Application
Code download
Packet Exchange
Receiver Timeout Helps to Support Variable Length Packets
Transmitter Time Guard helps to Support Slow Remote Devices
PDC Channel
ARM Core
ASB Arbiter
USART
RXRDY
PDC Receive Channel
RXEND
Size = Byte
TXRDY
PDC Transmit Channel
TXEND
Size = Byte
The PDC channels allow to transfert data from on-chip peripherals such as USART, SPI to on-chip memories without CPU intervention.Each USART channel is closely connected to a corresponding Peripheral Dedicated Controller channel. One is dedicated to the receiver, the other is dedicated to the transmitter.

30. SPI : Features Serial Interface between CPU and External Peripherals
Master or Slave Mode
Full duplex 3 wires synchronous transfer
MISO: Master In Slave Out
MOSI: Master Out Slave In
SPCK: SPI Clock
Maximum SPI baud rate clock: MCK/4
4 External Slave chip selects
8 to 16-bit Programmable Data Length
Mode Fault Detection in Master Mode
2 Dedicated PDC Channels
Depending on the device, the AT91 microcontroller can have up to 2 SPIs which provide communication with external devices in master or slave mode. The SPI has four external chip selects which can be connected to up to 15 devices. The data length is programmable, from 8 to 16-bit. As for the USART, a 2-channel PDC can be used to move data between memory and the SPI without CPU intervention.

31. SPI : Block Diagram

32. SPI : Bus Implementations
Up to 4 Peripherals
Up to 15 Peripherals with Decoding
AT91
AT91
SPI
SPI
4 to 16
Decoder
NPCS3
Q14
Serial
Peripheral
NPCS2
Serial
Peripheral
Q13
Serial
Peripheral
NPCS1
Serial
Peripheral
Q12
Serial
Peripheral
NPCS0
Serial
Peripheral
Q11
Serial
Peripheral
Serial
Peripheral
Q10
Serial
Peripheral Q1
Serial
Peripheral Q0
Serial
Peripheral
4 different protocols possible
First Bit set in NPCS field
4 different protocols possible
0-3, 4-7, 8-11, 12-14
Peripheral 15 is reserved for no selection

33. RTC : Real Time Clock (1/2)
Available on the AT91M55800A only
Features
Low power consumption
Complete time of day clock
Programmable periodic interrupts
Alarm
Five programmable fields: Month, Date, Sec, Min and Hour
Y2K compliant
BCD Format
The AT91M55800A features a Real Time Clock (RTC) peripheral that is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two hundred year calendar, complemented by a programmable periodic interrupt. The time and calendar value are coded in Binary Coded Decimal (BCD) format.

34. RTC : Real Time Clock (2/2)
Block Diagram

35. ADC : Analog to Digital Converter (1/2)
Available on the AT91M55800A only
Features
Two identical 4-channel ADC
10-bit resolution
Successive Approximation Register (SAR) approach
Settable analog input conversion range (dedicated VREF)
11 ADC clock cycles conversion time including 1 ADC clock cycle for sample and hold (e.g. 10µs for one channel at maximum clock rate)
4 LSB Maximum Integral Non-linearity
Sleep mode (energy saving)
Starting modes:
Software trigger
External input (A/D trigger)
Timers on-chip event signal
Dedicated analog power supply pins (VDDA and GNDA)
Improve noise rejection
End of conversion interrupt
The AT91M55800A features two identical 4-channel 10-bit Analog-to-digital converters (ADC) based on a Successive Approximation Register (SAR) approach.

36. ADC : Analog to Digital Converter (2/2)
Block Diagram
Each ADC has 4 analog input pins (AD0 to AD3 and AD4 to AD7), digital trigger input pins (AD0TRIG and AD1TRIG), and provides an interrupt signal to the AIC. Both ADCs share the analog power supply pins (VDDA and GNDA) and the input reference voltage pin (ADVREF).

37. DAC : Digital to Analog Converter (1/2)
Available on the AT91M55800A only
Features
Two identical 1-channel DAC
10-bit resolution
6µs maximum settling time
Settable analog output range (dedicated VREF)
4 LSB Maximum Integral Non-linearity
Starting modes:
software trigger
Timers on-chip event signal
Dedicated analog power supply pins (VDDA and GNDA)
Improve noise rejection
Data ready interrupt
The AT91M55800A features two identical 1-channel 10-bit Digital to Analoc Converters (DAC).

38. DAC : Digital to Analog Converter (2/2)
Block Diagram
Each DAC has an analog output pin (DA0 and DA1) and provides an interrupt signal to the AIC (DA0IRQ and DA1IRQ).