1. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 2: Introduction to Verilog Syntax Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

2. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l Labs start next week l HW#1 Due in 1 week l Verilog Simulation Tutorial (HW#4) Posted » Work through the first few pages to learn how to run Verilog simulations

3. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Summary of Last Lecture l Explain the differences between the following terms: » Schematic vs. Block Diagram » Port vs. Net » Symbol vs. Instance » System vs. Module » HDL vs. RTL

4. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 Today’s Lecture l Verilog Introduction l Conventions, Identifiers, Numbers, & Operators l Data Types l Modules l Test Benches

5. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 History of Verilog l 1984 – Developed by Gateway Design Automation l 1995 – Became an IEEE Standard (IEEE 1364-1995) l 2001 – Revised (IEEE 1364-2001) l 2003 – Accelera released the System Verilog 3.1 specification l In this class, we use both the IEEE 1364-1995 and IEEE 1364-2001 versions of the language. (Either will be accepted on your assignments).

6. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 Comparison of HDLs l Verilog » Most commonly used HDL in USA » Based on the C programming language » Least verbose » Fastest simulation l VHDL » Used by US Government, Europe, ASIA » Based on the ADA programming language » More general than Verilog l SystemC » Emerging Standard, used more for Electronic System Level (ESL) Descriptions » C++ class library that mimics VHDL, plus allows greater abstraction » Allows co-simulation of Hardware and Software

7. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 Today’s Lecture l Verilog Introduction l Conventions, Identifiers, Numbers, & Operators l Data Types l Modules l Test Benches

8. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 Example: Data Selector Route input data to one of two outputs. Specification: When a new data word arrives at the input, the module inspects the state of the most significant bit and routes the data to output A if the bit is true and to B if the bit is false. The last value sent to either output is retained until replaced. Data A-data B-data here new-A new-B A B

9. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Example: Stimulus l How to describe the module? l How to describe the stimulus? Data A-data B-data here new-A new-B A B

10. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 Verilog Language Conventions l Case sensitive l Whitespace ignored (except in strings) l Comments » Single Line: a = b && c; // The rest of this line is a comment » Multi-Line (cannot be nested): /* This is a multiple line comment*/

11. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 Identifiers l Can contain » Letters (a-z,A-Z) » Digits (0-9) » Underscore (_) » Dollar-sign ($) l Must start with a letter l Cannot be a keyword (see Sutherland, section 3.0 for a full list)

12. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 Operators l Unary - single operand » out = ~in l Binary - two operands » out = in1 && in2 l Ternary - three operands » out = select ? in1 : in2 l Nearly all Verilog statements end with a semicolon (don’t forget it on your homework)

13. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 13 Values l Write the following: » Binary 100111, 6 bits » Hex 7FFE, 16 bits » Decimal 133, 8 bits l Omitting gives an “unsized” value (32 bits) Sized numbers: ’ : specifies number of bits in number (in decimal) : decimal (‘d, ‘D); hexadecimal (‘h, ‘H); binary (‘b, ‘B); octal (‘o, ‘O) : digits (in base format) of the numeric value

14. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 14 Special Values Language conventions: Numbers & Values In addition to normal numeric values, Verilog provides two special values, x and z. x denotes an unknown or undefined value. z denotes a “high impedance” value l Write the following: » 16-bit hex, low order 4 bits unknown » 8-bit binary, high order 2 bits unknown » 8-bit value, all bits high impedance

15. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 15 Physical Meaning of Values Draw a circuit to represent the following values: 0 and 1 x

16. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 16 Physical Meaning of Values Draw a circuit to represent the following values: z

17. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 17 Values: Special Cases Zero fill / extension: If a numeric value does not contain enough digits to fill the specified number of bits, the high order bits are filled with zeros. If the most significant bit specified is an x or z, the x/z is left extended to fill the bit field. 16’h39  8’hz  Negative numbers: Specified by preceding the with a minus (negative) symbol. Values will be stored as the two’s complement of the given value.

18. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 18 Verilog 2001 Syntax l Signed Values: ’s l The “s” denotes that a value is signed (all other values are assumed unsigned) l This does not change the value, but it does change how certain operators deal with the value (namely, whether or not it will be sign-extended) l Examples: » 4’hF =1111 in binary » 4’shF = 1111 in binary (but will sometimes be interpreted as -1)

19. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 19 Example: Stimulus l How would you write the values for Data and here? (assume Data is 4 bits)

20. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 20 Today’s Lecture l Verilog Introduction l Conventions, Identifiers, Numbers, & Operators l Data Types l Modules l Test Benches

21. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 21 Net Variables Nets are usually declared by the keyword wire. Nets represent connections between hardware components. wire d;// declare output as net d. wire b, c;// declare two wires in same statement a, b, c, & d are nets. abab c d

22. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 22 Register Variables Registers are variables that can hold a value. not the same as a hardware register / flip-flop Registers can be assigned values multiple times during a simulation, but Nets can be assigned only at the beginning of a simulation. Would you use a Net or a Register variable for the Data and here signals in the Data Selector example? Registers are declared by the keyword reg. The default value for a reg data type is x. reg start; // declares register “start” reg reset, clock; // declares registers reset & clock

23. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 23 Vectors l Left bit is considered the most significant l By convention, use [ : ] Vectors can be specified by declaring the range of bit numbers with the variable name. The form of the declaration is: [ : ] ; or [ : ] ; // declare 8-bit data named BYTE // declare 16-bit register named INFO // declare 12-bit register named DATA

24. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 24 Specifying Parts of Vectors Given vector declarations, it is possible to reference parts of a register (down to a single bit). The format of the reference follows the pattern [ ]. // bit 5 of INFO // bits 11-8 of INFO (bits 11-8) // least significant byte of DATA

25. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 25 Other Types l Integer l Real l Time (accessed w/ system function $time) l Rarely used in the description of a hardware module but are frequently useful in the Test Bench. l See Sutherland, section 7.0 for details

26. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 26 Arrays Arrays can be declared for both scalar and vector data. An array is simply an ordered group of elements. All arrays are single dimensioned in Verilog. Arrays are declared with the syntax: [ ] or [ ] reg bool [31:0];// 32 1-bit boolean register values integer count [0:9];// array of 10 count variables reg [7:0] PID [0:5];// array of 6 bytes

27. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 27 Memories reg bitmem [0:1023]// 1K x 1 (bit) memory reg [7:0] MEM [0:16383]// 16K x 8 or 16K bytes Note that the addressing range is usually specified as [ : ] and for physical reasons, the address range starts at 0. Memories are defined by the syntax: [ ]

28. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 28 Symbolic Constants (Parameters) The parameter keyword allows definition of a symbolic label with a constant value. Anytime that label is used in the Verilog code, it is replaced with its constant value. parameter size = 16;// defines a constant called // size with a value of 16 For example, if size is defined with a value of 16, the memory declaration: reg [size-1 : 0] MEM [0 : 4095] gives the same result as writing: reg [15:0] MEM [0:4095]

29. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 29 Verilog 2001 Syntax l Signed Variables can be declared with the keyword signed l As with signed values, declaring a variable as signed does not change its value, but rather how certain operators deal with the value (namely, whether or not it will be sign-extended) reg signed [7:0] mybyte; wire signed [5:0] myvar;

30. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 30 Today’s Lecture l Verilog Introduction l Conventions, Identifiers, Numbers, & Operators l Data Types l Modules l Test Benches

31. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 31 Module Descriptions in Verilog The Verilog description of a digital module follows a prescribed structure as follows: Header Port declarations Variable declarations Instantiation of lower-level modules Functionality description - Gate-level - Data Flow - Behavioral Terminator Let’s write a module description for the Data Selector:

32. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 32 Header & Port Declarations Module header: names the module and lists ports. module ( ); Port declarations: specify the input and output port characteristics. (like variable declarations, but use the keywords input and output)

33. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 33 Variable Declarations Variable declarations: specify module’s nets & registers. reg [15:0] A, B;// A & B are 16-bit registers wire [15:0] Data, A_data, B_data; wire here, new_A, new_B; Note: The wire declarations could be omitted since port declarations imply the associated nets.

34. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 34 Verilog 2001 Syntax l Verilog 2001 allows port declarations within the port-list module data_selector (Data, here, A_data, new_A, B_data, new_B); input [15:0] Data; input here; output [15:0] A_data, B_data; output new_A, new_B; module data_selector ( input [15:0] Data, input here, output [15:0] A_data, B_data, output new_A, new_B ); 1995 Syntax 2001 Syntax

35. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 35 Instantiation, Functionality, Terminator Terminator marks the end of the Verilog module description. It is simply endmodule (without a trailing semicolon). Instantiation of lower-level modules: creates a unique named instance for each of the low-level modules. ( ); Functionality description: specifies the internal organization and operation of the module. There are three levels of abstraction that will be studied:

36. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 36 Data Selector’s Module Description module data_selector (Data, here, A_data, new_A, B_data, new_B); input [15:0] Data; input here; output [15:0] A_data, B_data; output new_A, new_B; reg [15:0] A, B; wire [15:0] DATA, A_data, B_data;// these 2 lines can wire here, new_A, new_B;// be omitted // No modules to instantiate for this design // Description of functionality would go here endmodule 1995 Syntax

37. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 37 Data Selector’s Module Description module data_selector (input [15:0] Data, input here, output [15:0] A_data, B_data, output new_A, new_B); reg [15:0] A, B; // No modules to instantiate for this design // Description of functionality would go here endmodule 2001 Syntax

38. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 38 Today’s Lecture l Verilog Introduction l Conventions, Identifiers, Numbers, & Operators l Data Types l Modules l Test Benches

39. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 39 Creating the Stimulus l We know how to describe the Data-Selector, but how do we describe its stimulus? l Need to specify a behavior that has a beginning and an end.

40. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 40 Initial Blocks l Use an initial block to specify a behavior for a module that executes once at the beginning of the simulation. initial begin myvar = 4’d9; myvar = 4’d7; … end l begin and end are needed only if there is more than one statement in the initial block (like “{“ and “}” in C) l Note that there is no semicolon after initial, begin, end l In the example above, is myvar declared as wire or reg?

41. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 41 Displaying Values l Use the system task $display to print out values l $display is like printf() in C (see Sutherland, section 18.0 for details) module hello; initial $display(“Hello World!\n”); endmodule //hello

42. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 42 Representation of Stimulus module test; reg [3:0] Data; initial begin Data = 4'h2; $display("Data = %h",Data); Data = 4'hA; $display("Data = %h",Data); Data = 4'h7; $display("Data = %h",Data); end endmodule //test

43. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 43 Summary l What characters are allowed in identifiers? l What kinds of circuits would generate the values 0, 1, x, and z? l What is the difference between wire and reg variables? l What parts of the module description do you need to create a test-bench?

44. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 44 Homework #1 Tips l Problem 2 (a) and (b) » Please convert to binary manually l Problem 7 » See Sutherland, section 19.0 for an example of the `define compiler directive