1. EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009 Static Timing Analysis and Gate Sizing

2. 2015/10/5 PJF- 2Circuit Delay Delay Evaluation 1. Gate delay 1. Gate delay 2. Interconnect delay 2. Interconnect delay

3. 2015/10/5 PJF- 3Circuit Delay 1. Problem Description Given a pair of pins, compute pin-to-pin delay and possibly output waveform Given a pair of pins, compute pin-to-pin delay and possibly output waveform Cell Delay Interconnect Cell …

4. 2015/10/5 PJF- 4Circuit Delay Circuit Model For an inverter For an inverter Csink … …

5. 2015/10/5 PJF- 5Circuit Delay Sink Capacitance Gate capacitance, input capacitance Gate capacitance, input capacitance Given for standard cells Given for standard cells Can be found using SPICE Can be found using SPICE Apply an AC voltage and measure current Apply an AC voltage and measure current Average over a range of frequency Average over a range of frequency I

6. 2015/10/5 PJF- 6Circuit Delay Capacitance Model Ctotal Rd RC

7. 2015/10/5 PJF- 7Circuit Delay Interconnect Delay: Elmore Delay Elmore is used as the delay on interconnect Elmore is used as the delay on interconnect Easy to compute Easy to compute

8. 2015/10/5 PJF- 8Circuit Delay Example 1 11 1 1 1 1 1 4 231 m 1_1 = –4, m 1_2 = –7, m 1_3 = –8, m 1_4 = –8

9. 2015/10/5 PJF- 9Circuit Delay Application of Elmore Delay Good Good Closed form expression, easy to compute Closed form expression, easy to compute Useful in circuit design such as gate sizing and buffering. Useful in circuit design such as gate sizing and buffering. Bad Bad Inaccurate Inaccurate Not useful for timing verification Not useful for timing verification

10. 2015/10/5 PJF- 10Circuit Delay Circuit Delay Evaluation - Two Components Cell delay + interconnect delay Cell delay + interconnect delay Cell delay is computed using RC or K- factor Cell delay is computed using RC or K- factor Interconnect delay is computed using Elmore delay Interconnect delay is computed using Elmore delay Cell Interconnect

11. 2015/10/5 PJF- 11Circuit Delay Static vs. Dynamic Timing Analysis Static timing analysis Static timing analysis Fast Fast Consider all paths Consider all paths Pessimism by considering false paths which are never exercised Pessimism by considering false paths which are never exercised Dynamic timing analysis ( simulation ) Depends on input stimulus vectors Do not report timing on false paths With large number of testing vectors Accurate Slow

12. 12 Wire and Gate Models

13. Step by Step 2015/10/5 PJF- 13Circuit Delay Model combinational circuit using the previous slide Model combinational circuit using the previous slide Starting from primary input gates, compute the arrival time (AT) at each gate, i.e., compute gate delay and interconnect delay Starting from primary input gates, compute the arrival time (AT) at each gate, i.e., compute gate delay and interconnect delay In order to compute the AT at a gate, the ATs of all its input gates need to be computed In order to compute the AT at a gate, the ATs of all its input gates need to be computed Repeat the above process until the ATs at all primary output gates are computed Repeat the above process until the ATs at all primary output gates are computed

14. 2015/10/5 PJF- 14Circuit Delay Example of Static Timing Analysis Arrival time (AT): input -> output, take max Arrival time (AT): input -> output, take max 1 3 2 4 5

15. 2015/10/5 PJF- 15Circuit Delay Timing Optimization Arrival time (AT): input -> output, take max Arrival time (AT): input -> output, take max Should we size up this gate to improve timing?

16. 2015/10/5 PJF- 16Circuit Delay Timing Optimization- II Suppose that we have a gate (with same gate type) doubling its width. We roughly have C=10, R=1. Suppose that we have a gate (with same gate type) doubling its width. We roughly have C=10, R=1. If we change the gate with this new one, what is the new delay? Does not change If we change the gate with this new one, what is the new delay? Does not change

17. 2015/10/5 PJF- 17Circuit Delay Timing Optimization- III Suppose that we have a gate (with same gate type) doubling its width. We roughly have C=8, R=1. Suppose that we have a gate (with same gate type) doubling its width. We roughly have C=8, R=1. If we change the gate with this new one, what is the new delay? If we change the gate with this new one, what is the new delay?

18. 2015/10/5 PJF- 18Circuit Delay Timing Optimization- IV This optimization is called gate sizing. Change the gate size (width) in optimization. This optimization is called gate sizing. Change the gate size (width) in optimization. 1. Given multiple choices (implementations) per gate type, find a gate implementation at each gate such that the circuit timing is minimized. 1. Given multiple choices (implementations) per gate type, find a gate implementation at each gate such that the circuit timing is minimized. 2. Given multiple choices per gate type, find a gate implementation at each gate such that the circuit timing satisfies the target and the total gate area/power is minimized 2. Given multiple choices per gate type, find a gate implementation at each gate such that the circuit timing satisfies the target and the total gate area/power is minimized

19. Problem Definition of Gate Sizing Given a timing (delay) target, use smallest power/area gates to meet the timing target Given a timing (delay) target, use smallest power/area gates to meet the timing target In general, smaller power -> larger timing, smaller timing -> larger power. In general, smaller power -> larger timing, smaller timing -> larger power. 19

20. 20 Delay due to Gate Sizing Suppose that unit width gate capacitance is c and unit width gate resistance is r. Given gate size w i, Suppose that unit width gate capacitance is c and unit width gate resistance is r. Given gate size w i, Gate size w i : R  r/w i, C  cw i Gate size w i : R  r/w i, C  cw i Delay is a function of RC Delay is a function of RC Delay   R i C j   w i /w j Delay   R i C j   w i /w j

21. 21 Wire and Gate Models

22. 22 Combinatorial Circuit Model Gate size variables x 1, x 2, x 3 Gate size variables x 1, x 2, x 3 Delay on each gate depends on x Delay on each gate depends on x DriversLoads x2x2 x3x3 x1x1 a3a3 a4a4 a5a5 a1a1 a2a2 D1D1 D3D3 D2D2 D5D5 D4D4 D7D7 D6D6 D9D9 D8D8 D 10 a6a6 a7a7

23. 23 Path Delay Express path delay in terms of component delay Express path delay in terms of component delay A component can be a gate or a wire A component can be a gate or a wire Delay D for each component Delay D for each component Arrival time a for some components Arrival time a for some components

24. 24 Gate Sizing Power/area minimization under delay constraints: Power/area minimization under delay constraints: This can be solved efficiently using gpsolve This can be solved efficiently using gpsolve

25. Gate Sizing using GPSOLVE Follow the steps in gatesizing.m Follow the steps in gatesizing.m 25