1. 1 Nios II Processor Architecture and Programming CEG 4131 Computer Architecture III Miodrag Bolic

2. 2 Presentation Outline Basic description of Stratix Altera Devices NIOS II processor architecture –Review pipelining techniques –Review memory access techniques How to design a system using NIOS II processor

3. 3 Stratix EP1S10 [2]

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6. 6 TriMatrix™ Memory [1] M512 Blocks M4K Blocks M-RAM Dedicated External Memory Interface Look-Up Schemes Packet & Cell Buffering Cache More Bits For Larger Memory Buffering More Data Ports for Greater Memory Bandwidth Small FIFOs Shift Register Rake Receiver Correlator FIR Filter Delay Line Header / Cell Storage Channelized Functions ATM cell–packet processing Nios Program Memory Packet / Data Storage Nios Program Memory System Cache Video Frame Buffers Echo Canceller Data Storage 512 bits per block + parity 4 Kbits per block + parity 512 Kbits per block + parity

7. 7 Memory Bandwidth Summary Stratix Device Family [1] DeviceTotal RAM Bits M-RAM Blocks M4K BlocksM512 Blocks Maximum Bandwidth (Mbps) EP1S10920,448160941,245,024 EP1S201,669,2482821942,096,928 EP1S251,944,57621382242,894,400 EP1S303,317,18441712953,750,192 EP1S403,423,74441833844,384,800 EP1S605,215,10462925746,762,528 EP1S807,427,52093647678,784,720

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9. 9 Logic Element (LE) [2] Sync Load & Clear Logic D DATA 4-Input LUT Register Control Signals Register Chain Input Register Chain Output LUT Chain Output data1 data2 data3 data4 cin Row, Column & DirectLink Routing Local Routing Note: 1)Functional Diagram Only. Please See Datasheet for more Details. 2)Addnsum & data1 connected via XOR logic LUT Chain Input Register Feedback addnsub (2)

10. 10 Logic Array Blocks (LAB) [2] 10 LEs Local Interconnect LAB-Wide Control Signals LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8 LE10 LE9 4 4 4 4 4 4 4 4 4 4 Control Signals Local Interconnect

11. 11 Presentation Outline Basic description of Stratix Altera Devices NIOS II processor architecture –Review pipelining techniques –Review memory access techniques How to design a system using NIOS II processor

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13. 13 NIOS II Overview [3] Soft IP Core –A soft-core processor is a microprocessor fully described in software, usually in an HDL, which can be synthesized in programmable hardware, such as FPGAs. Reduced Instruction Set Computer (RISC) No pipeline, 5 or 6 stages pipeline configurations Full 32-bit instruction set, data path, and address space 32 general-purpose registers 32 external interrupt sources Access to a variety of on-chip peripherals, and interfaces to off-chip memories and peripherals Software development environment based on the GNU C/C++ tool chain and Eclipse IDE

14. 14 NIOS II Scalability Powerful multiprocessing systems can be built

15. 15 NIOS II Processor Core [3]

16. 16 Implementation The functional units of the Nios II architecture form the foundation for the Nios II instruction set. The Nios II architecture describes an instruction set, not a particular hardware implementation. Trade-offs: –More or less of a feature - amount of instruction cache memory. –Inclusion or exclusion of a feature - the JTAG debug module. –Hardware implementation or software emulation - divider

17. 17 Types of Processors

18. 18 Memory Organization

19. 19 Instruction and Data Cache Useful for high latency external memories Cache is direct mapped –Low address bits represent cache line Use write-though policy –Data is written to external memory as well as cache Problem –Instruction cache has 32 bytes per cache line –We choose cache size of 1024 bytes –Question: How many bits are needed for the tag

20. 20 Cache Performance MemoryI-CacheD-CacheNormalised Performance SDRAMNoNo40.2% SDRAMNoYes55.2% SDRAMYesNo64.3% SDRAMYesYes96.4% OnChipNoNo100.0% OnChipNoYes98.0% OnChipYesNo110.2% OnChipYesYes105.6% Performance relative to on chip RAM with no Cache running dhry.c modified for unbuffered I/O MemoryI-CacheD-CacheNormalised Performance SDRAMNoNo40.2% SDRAMNoYes55.2% SDRAMYesNo64.3% SDRAMYesYes96.4% OnChipNoNo100.0% OnChipNoYes98.0% OnChipYesNo110.2% OnChipYesYes105.6%

21. 21 Tightly Coupled Memory Fast data buffers Fast sections of code Fast interrupt handler Critical loop Constant access time; guaranteed not to have arbitration delays Up to 4 tightly coupled memories Software Guidelines –Software accesses tightly-coupled memory addresses just like any other addresses. –Cache operations have no effect when targeting tightly-coupled

22. 22 Pipelining Static branch prediction is implemented using the branch offset direction; –a negative offset is predicted as taken –a positive offset is predicted as not-taken

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24. 24 Presentation Outline Basic description of Stratix Altera Devices NIOS II processor architecture –Review pipelining techniques –Review memory access techniques How to design a system using NIOS II processor

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26. 26 Hardware Abstraction Layer (HAL) [4] Isolates the application software from hardware modifications. Applications are device-independent because they abstract information from such systems as: –Character mode devices: UART core, JTAG UART core, LCD display controller –Flash memory devices –Timer devices –DMA controller core –Ethernet MAC/PHY Controller HAL application program interface (API) is integrated with the ANSI C standard library.

27. 27 Layers of HAL API [4] HAL library generatioin: 1.SOPC Builder generates a hardware system 2.Nios II IDE generates a custom HAL system library to match the hardware configuration Changes in the hardware configuration automatically propagate to the HAL device driver configuration NIOS II is programmed in C

28. 28 Programming NIOS II Processor [4] Programming UART –Standard Input, Standard Output routines in C --------------------------------------------------- #include int main (void) { char* msg = “hello world”; FILE* fp; fp = fopen (“/dev/uart1”, “w”); if (fp) { fprintf(fp, “%s”,msg); fclose (fp); } return 0; } ---------------------------------------------------

29. 29 References 1.Altera Corp., Stratix & Stratix II Module 3: Using TriMatrix Memories, 2004 2.Altera Corp., Stratix Module 2: Logic Structure & MultiTrack Interconnect, 2004. 3.Altera Corp., Nios II Processor Reference Handbook, 2005.Nios II Processor Reference Handbook 4.Altera Corp., Nios II Software Developer's Handbook, 2005.Nios II Software Developer's Handbook