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Wade Pentz Blake Orth Grant Fritz Andrew Gunn Brian Weinstein

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Presentation on theme: "Wade Pentz Blake Orth Grant Fritz Andrew Gunn Brian Weinstein"— Presentation transcript:

1 Wade Pentz Blake Orth Grant Fritz Andrew Gunn Brian Weinstein
TRI-ADS: Targeted Remote Information and Advertisement Distribution System Wade Pentz Blake Orth Grant Fritz Andrew Gunn Brian Weinstein

2 System Overview Network of targeted advertisement display modules
Change display based on location, time of day, weather, emergency status, etc Provide standard DVI output Modules communicate wirelessly with a base station Powered from 12V DC wall adapter or car outlet Wade Pentz

3 System Overview Wade Wade Pentz

4 Primary Secondary Tertiary GPS data processing LCD display
GPS based image change Primary WiFi communication Base station Secondary Andrew Universal power board Base station GUI Second module Packaging Analog sensors Animation Bluetooth Tertiary

5 Level 0 Functional Decomposition
Wade Pentz

6 Level 1Hardware Functional Decomposition
Wade – NEEDS EDIT Wade Pentz

7 Command and Data Handling System Overview
Coordinate DVI output with CPLD and load image off of SD card Store GPS location and coordinate ad changes Manage Wifi/3G link and remote update Manage Bluetooth communications between display modules Gather temperature/accelerometer data and coordinate ad changes Grant Grant Fritz

8 CDH Functional Decomposition
Grant Fritz

9 Command and Data Handling System Hardware
Using NGW-100 as main board AT32AP7000 microprocessor 2.6 Linux Kernel Resource Management Modular process software design Utilize standard libraries Grant Grant Fritz

10 Software Functional Diagram
Grant – NEEDS Updated functional diagram or replacement by sft functional decomp Grant Fritz

11 CDH Software Functional Decomposition
Grant Fritz

12 Level 1 Software Decomposition
Grant Fritz

13 CDH SFT Functional Decomposition
Grant Fritz

14 Display System Overview
Use DVI for easy interface to screens of various sizes DVI prioritized over VGA to allow for future expandability Custom display hardware will allow for a simple embedded solution Removes the need to interface and power a full rendering graphics card Current image stored to on-board SRAM for fast access Will be implemented using TFP410 DVI Trasmitter, Altera MaxII CPLD and 6MB SRAM Blake Blake Orth

15 Display Functional Decomposition
Blake Orth

16 CPLD Programmed using Verilog through JTAG Clocked at 165MHz
Takes care of all Video memory Operations Reads pixel data from SRAM chips and presents it at 24-bit DVI chip input Write new image data to SRAM chips Receives new image data from the microcontroller via SPI Manage all SRAM and DVI control lines Blake Orth

17 EPM570T144C5N Max II – 570 Series 144-TQFP
Selected for fast pin-to-pin propagation delay ( down to 4.5ns) 440 macro-cells allows for reasonably complex logic Good performance for current draw – at most draws 250mA Development board being used to develop Verilog code Blake Orth

18 Display System Hardware
Use TI TFP410 PanelBus DVI Transmitter Blake Blake Orth

19 TI TFP410 DVI Transmitter Basic configuration through I2C
Allows settings for resolution, DE generator, and data de-skew Takes 24-bit True Color pixel data and control signals Encodes and serializes pixel data to PanelBus DVI and outputs to a standard Single Link DVI Connector Blake Orth

20 SRAM Stores current image data (1 image) Three SRAM units will be used
24-bit True Color for each pixel 8-bits for each color part (RGB) Three SRAM units will be used RGB pixel data stored in parallel One unit for each color Shared 20-bit address bus All parts of a single pixel will have a shared address Shared 8-bit data bus Bus control handled with output/write enable pins Blake Orth

21 SRAM Selection ISSI IS61WV102416 1M x 16b SRAM 8 ns access time
Using 3 modules totals to 6MB of storage Blake Orth

22 SRAM Modes SRAM has ability for 16-bit data bus
We are using in 8-bit data bus mode 20-bit address selects a 16-bit word Uses /LB and /UB pins to select upper or lower byte Blake Orth

23 Read Cycle Timing Diagram
Notes: - Upper/Lower byte selection control pins not shown here - /CE will be tied active Blake Orth

24

25

26 Brian

27 COM Functional Decomposition
Andrew Andrew Gunn

28 GPS Primary Objective GPS location used to provide optimal advertisement RS232 Interface GPS Handler script Input a character string Outputs global variables taken from the char string Andrew Andrew Gunn

29 GPS Handler Type = GPGGA Time = 18hr 41min 49secs Zulu Time
$GPGGA, , ,N, ,W,1,05,1.68,01633,M,-020,M,,*5C Type = GPGGA Time = 18hr 41min 49secs Zulu Time North Latitude West Longitude GPS Quality 0=No GPS, 1=GPS, 2=DGPS Number of Satellites 5 Altitude in Meters 01633 Andrew Andrew Gunn

30 GPS Status Update Where From Here Full Circle & Fully Functional
GPS Module Receives Data From Satellites Microprocessor Receives Data String GPS Handler Parses & Saves Information Where From Here Implement Position Logic If in this Location -> Display This Ad Andrew Gunn

31 Wifi Used to update the Display Module with new advertisements & information Initial Wifly utilizes telnet exclusively Telnet is completely unsecure Telnet is Great for sending small strings across local network but not so great at sending large files over internet. Breakdown, Encrypt, Pack, Transmit, Decrypt, Unpack In addition to writing the serial and wifi drivers Andrew Andrew Gunn

32 Wiport Wifi Module Interface RS 232 to UART or Ethernet
Wiport - Breakdown, Encrypt, Pack, Transmit, Decrypt, Unpack Serial and Wifi Drivers Wifi Software Input a character string to change networks Outputs information or files through Ethernet Andrew Gunn

33 Bluetooth Tertiary objective
RS232 thus we can reuse serial driver from GPS Milestone 2 objective Overall COM Board Connects module headers to board stacks Board Designed in Altium in progress Andrew Gunn

34 Power Functional Decomposition
Wade Pentz

35 Power System Each board has its own power stage
Allows each board to be tested separately Uses linear regulator to provide needed voltage rails All IC’s use 3.3V If time allows, a power board will be created Route IC power Provide DVI display power using boost converter Wade Pentz

36 Power Stage Power switch for each board Bridge rectifier IC (DF10S)
1.5 Amp average current rating 1.1 Volt forward drop LM317 adjustable linear regulator Uses voltage divider to set output voltage Extremely accurate regulation Additional protection diodes Wade Pentz

37 Power Stage Wade Pentz

38 LM317 Linear Regulator Circuit
For 3.3V: R1 = 220 Ohms R2 = 330 Ohms Brian

39 Base Station Current Status Where we want to go Image_Handler
Hi Res. Display Outbox Base Station Image_handler Ad Uploaded Current Status Image_Handler Converts input to JPG Multiple Copies based on Resolution Places in Outbox Auto SSH with RSA Pushing configurations & images to display units Where we want to go Optimize and increase functionality GUI if time allows Low Res. Display Andrew Gunn

40 Milestone 1 System Milestone 2 Serial Driver I2C Driver GPS Driver Wifi Driver Skeleton framework CDH CDH CPLD SPI interface JPEG conversion and display Wireless image download Display Display Board populated CPLD programmable Initial CPLD code written Write to and read from SRAM Interface with DVI chip Update image based on location COM Comm Bluetooth working Receive image updates through wifi Send updates to basestation Wifi working GPS working Board populated Power Power Individual board power functional Power board (tentative)

41 Expo Complete system working User’s manual Display images through DVI
Change images based on location All devices talking with CDH Full communication with base station over wireless Bluetooth communication functional Power board if necessary and time allows Second module if time allows User’s manual Brian Weinstein

42 Division of Labor Task Wade Andrew Grant Blake Brian CDH Software
Secondary Primary EPS Board DVI Board Layout CPLD Software COM Board COM Software ( DHCP, SSH, etc) COM Firmware (Wifi, GPS, Bluetooth) Base Station Programming Documentation Blake Brian Weinstein

43 Schedule Blake Brian Weinstein

44 Schedule Highlights CPLD Code Development Begins
Goal: Monday February 28th Order Display and Com Boards Goal: March 1st Schedule Multitasking and Dependencies Integration of Hardware and Software Brian Weinstein

45 Budget Item Cost NGW100 Dev Board $120 Board Fabrication
DVI Chip (TFP410) $7.50 GPS with Breakout Board $116.90 Bluetooth $74.95 Wiport $123 SRAM x 3 $75 CPLD $6 Miscellaneous Components $100 Printing Expenses Sub-Total $738.35 UROP Funding $-960 Sparkfun Donation $-150 Total $ Blake Brian Weinstein

46 Risk Management (303) 55-RILEY Risk Blake Brian Weinstein

47 Questions? Thank you! Blake


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