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ALL-OPTICAL PACKET HEADER PROCESSING SCHEME BASED ON PULSE POSITION MODULATION IN PACKET-SWITCHED NETWORKS Z. Ghassemlooy, H. Le Minh, Wai Pang Ng Optical.

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Presentation on theme: "ALL-OPTICAL PACKET HEADER PROCESSING SCHEME BASED ON PULSE POSITION MODULATION IN PACKET-SWITCHED NETWORKS Z. Ghassemlooy, H. Le Minh, Wai Pang Ng Optical."— Presentation transcript:

1 ALL-OPTICAL PACKET HEADER PROCESSING SCHEME BASED ON PULSE POSITION MODULATION IN PACKET-SWITCHED NETWORKS Z. Ghassemlooy, H. Le Minh, Wai Pang Ng Optical Communications Research Group Northumbria University, UK http://soe.unn.ac.uk/ocr/

2 Contents Overview of header processing in optical networks Header processing based on pulse-position modulation (PPM) Proposed node architecture Simulation results Summary

3 Optical Communication Network (OCN)  Solution: All-optical processing & switching 1P 100T 10T 1T 100G 10G 1G 100M 1995 2000 2005 2010 Year Demand traffic [bit/s] Voice Data Total NEC-2001 - Future OCNs: faster signal processing and switching to cope with the increase of the demanding network traffic - Existing OCNs: depends on electronic devices for processing the packet address to obtain the routing path. However, the limitation of electronic response will cause the speed bottleneck

4 Future OCNs Optical transparent path - Future OCN will have the processing and switching data packets entirely in optical domain, i.e. generate optical transparent path for routing data packets  Require: compact and scalable processing scheme

5 Current All-optical Processing Schemes All-optical logic gates All-optical correlators Address patterns Decimal value Output ports 0 0 0Port 2 0 0 0 11Port 1 0 0 1 02Port 3 0 0 1 13Port 1 0 1 0 04Port 3 0 1 5Port 2 0 1 1 06Port 2 0 1 1 17Port 1 1 0 0 08Port 3 1 0 0 19Port 2 1 0 Port 2 1 0 1 111Port 3 1 1 0 012Port 1 1 1 0 113Port 1 1 1 1 014Port 2 1 1 15Port 1 Routing table (RT) Example: N = 4, node with M = 3 ? Port 1 Port 2 Port 3 N-bit Problems: Large size routing table  increased processing time Optical device complexity  poor scalability Solution: To reduce the size of the routing table

6 PPM - Operation Address extraction a 0 a 1 a 2 a 3 payload Header (packet address) Clk Data packet PPM (a)(b) (a)(b)

7 PPM Based Routing Table Grouping address patterns having the same output ports Each new pulse-position routing table (PPRT) entry has optical pulses at the positions corresponding to the decimal values of group’s patterns Pulse-position routing table (N = 4, M = 3)

8 Header Correlation Single AND operation is required for matching PPM-address and multiple address patterns (PPRT entry) Processing-time gain:

9 Proposed Node with PPM Processing Clock extraction: synchronize the arrival of data packet and the node processing S-P converter: convert the serial address bits to parallel bits PPM-ACM: (PPM address conversion module): convert binary address to the PPM-converted address PPRT: store M entries (M PPM frames) Switch synchronisation: synchronise SW with data packet All-optical switch: controlled by matching signals to open the correct SW Clock extraction S-P Converter PPM-ACM & M SW1 SW2 SWM Header processing unit 1 2 M All-optical switch... Data H C lk PPRT Entry 1 Entry 2 Entry M... & 1 & 2 Switch Sync. Data H C lk H

10 PPRT with Multimode Transmission Same address pattern can appear at multiple PPRT entries Modes: unicast, multicast, broadcast and deletion Pulse-position routing table (N = 4, M = 3)

11 Node with Multicast Tx Mode Clock extraction S-P Converter PPM-ACM & M SW1 SW2 SWM Header processing unit 1 2 M All-optical switch... Data H C lk PPRT Entry 1 Entry 2 Entry M... & 1 & 2 Switch Sync. Data H C lk H Data H C lk

12 Optical PPM Generation Circuit PPM-format address: y(t) = x(t +  i a i  2 i  T s ) N-bit address-codeword: A = [a i  {0,1}], i = 0, …, N–1

13 PPRT Generation Is self-initialised with the extracted clock pulse. The M entries are filled by: – Single optical pulse + Array of 2 N optical delay lines; Or, – M pattern generators + M optical modulators.

14 Ultrafast Optical AND Gate A/B01 000 101 Implementation: Using optical interferometer configuration + optical nonlinear devices A B A×BA×B SOA1 SOA2 Symmetric Mach-Zehnder Interferometer (SMZI)

15 All-Optical Switch 1 M1 M SMZ-1 SMZ-2 SMZ-M … CP1 CP2 CPM 1 2 M

16 Simulation Results Simulation parameters Values Address length N5 Number of outputs M3 Bit rate50 Gb/s Payload16 bits Packet gap2 ns Pulse width FWHM1 ps Pulse’s power peak2 mW Wavelength1554 nm PPM slot duration T s 5 ps For an all-optical core network up to 2 5 = 32 nodes

17 Simulation Results Demonstrate the PPM processing and Tx modes PPRT with 3 entries:

18 Simulation Results Input Output 1 Output 2 Output 3

19 Simulation Results 0 1 1 1 0 Packet with address 01110 PPM-converted address PPRT entry 1 Synchronized matching pulse

20 Conclusions PPM processing scheme – Reduces the required processing time – Provides the scalability: adding/dropping network nodes and node outputs Applications: – All-optical core/backbone networks (N >> M ~ 3-6) – Optical bypass router (electrical router + optical bypass router) Challenges: – Optical switch with long and variable switching window – Timing jitter and received pulse dispersion

21 Publications H. Le-Minh, Z. Ghassemlooy, and W. P. Ng., “A novel node architecture for all-optical packet switched network”, proceeding of 10 th European Conference on Networks and Optical Communications 2005 (NOC2005), pp. 209-216, London, UK, Jul. 2005 H. Le-Minh, Z. Ghassemlooy, and W. P. Ng., ”Ultrafast header processing in all-optical packet switched-network” proceeding of 7 th International Conference on Transparent Optical Networks 2005 (ICTON2005), Vol. 2, pp. 50-53, Barcelona, Spain, Jul. 2005

22 Acknowledgements Northumbria University for sponsoring the research work

23 Thank you!


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