1. Nurudeen Olayiwola Thomas Gutierrez
General Info
Purpose/ Applications
Interrupts
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Nurudeen Olayiwola
Thomas Gutierrez
Non-maskable interrupts
Example
Conclusion

2. Question??
General Info
Purpose/ Applications
When you are at home sitting on your lazy boy, how do you know when someone wants to talk to you on the phone?
Do you periodically get up and pick up the phone to see if someone is there?
Or do you wait till the phone rings to answer it?
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

3. Answer?
General Info
Purpose/ Applications
The first scenario shows a person doing what is known as polling.
The second case illustrates an interrupt-driven person.
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

4. Polling AKA “busy waiting”; looping program
General Info
Purpose/ Applications
AKA “busy waiting”; looping program
Continues checking status register until a particular state exists
“Are we there yet? Are we there yet? Are we there yet?”
What happens if something occurs at other devices while the processor is busy waiting??
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

5. Interrupt Device sends a special signal to CPU when data arrives.
General Info
Purpose/ Applications
Device sends a special signal to CPU when data arrives.
“Wake me up when we get there.”
Responds to hardware interrupt signal by interrupting current processing.
Now CPU can perform tasks before and after interrupt instead of just polling!! Good!
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

6. General Interrupt Flow
General Info
Purpose/ Applications
Completes current instruction
Saves current state to status registers
Identify source
Jump to and activate Interrupt Service Routing (ISR)
Return to original program (RTI) and restore state
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Register
CPU
Interrupt driven
Example
I/O
device
I/O
device

7. Interrupts: Flow Chart
General Info
SOFTWARE
INTERRUPT
STACK MPU REGISTER CONTENTS
SET APPROPRIATE BIT IN CCR
LOAD INTERRUPT VECTOR INTO PROGRAM COUNTER
VECTOR TABLE
HARDWARE
MASK SET? N Y
EXECUTE INTERRUPT SERVICE ROUTINE
$FFC0
$FFFF
CONTINUE MAIN PROGRAM

8. Brief Background
General Info
Purpose/ Applications
Univac 1103/1103A ( ) – first recognized CPU with interrupts. Current instruction was stored in memory and program counter loaded with a fixed address.
Other notables:
IBM (1954) – first to use interrupt masking
NBS DYSEAC (1954) – first with I/O interrupts
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

9. Purpose/Applications
General Info
Purpose/ Applications
To modify or do additional instructions based on internal requests and/or external devices.
Provide a means for suspending current instructions for more important tasks.
Hardware (called Interrupts or Resets)
Reset
User-defined interrupt
Timer operations
CPU operations monitor failure
Software
Illegal instruction
SWI
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

10. Purpose/Applications (cont.)
General Info
Purpose/ Applications
Coordinating I/O operations
Notifies the CPU that an input is ready or an output can be changed
Timing
Periodic (clock-driven) interrupts remind the CPU of the passage of time
Multi-tasking
Updating counters
Timing during interactive programs
Errors
Interrupts can notify of error situations
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

11. Purpose/Applications (cont.)
General Info
Purpose/ Applications
Practical uses/examples
Change direction of a motor.
Auto wiper speed increased or decreased.
Pressing a pause button on a VCR
HC11 controlled transmission system
Etc.
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

12. Types of interrupts Ignorable interrupts (or Maskable)
General Info
Purpose/ Applications
Ignorable interrupts (or Maskable)
Most often used
Good for using when computer needs to do something more important
When the interrupt mask is set, interrupts are hidden and therefore are ignored.
Non-ignorable interrupts (Non-maskable)
NMI’s take precedence and interrupt any task
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

13. Interrupt Vector Table
General Info
Purpose/ Applications
When an interrupt occurs, control of the program moves to the interrupt handling routine
Event similar to subroutine
How do we know where the handler routine is though??
The address of the handler is provided by the interrupt vector table
IVT has one entry for each type of interrupt
Each entry is indexed by interrupt type, and includes a pointer to the handler
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

14. Interrupt Vector Table
Maskable when the I-bit of CCR is set
Interrupt Vector Table
General Info
Purpose/ Applications
lowest priority
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example
highest priority
Unmaskable

15. Maskable/Unmaskable 6 Non-Maskable
General Info
Purpose/ Applications
6 Non-Maskable
always interrupt the program execution
15 Maskable
can enable or disable by mask bits
HOW?
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

16. Stacking order General Info Purpose/ Applications
When an interrupt occurs:
Purpose/ Applications
SP-9
1. Finish execution of the current instruction Note: Non-maskable interrupts and resets happen immediately
SP-8
CCR
Interrupt Priority/ IVT
SP-7
ACCB
SP-6
ACCA
2. HC11 pushes on stack: PC, accumulators and registers, CCR
SP-5
IXH
Controlling Interrupts
SP-4
IXL
SP-3
IYH
3. HC11 sets the I-bit Masks interrupts - can’t interrupt an interrupt
Maskable interrupts
SP-2
IYL
SP-1
PCH
4. Looks up vector of highest-priority interrupt
SP-0
PCL
5. Branches to interrupt service routine
Executes until RTI is encountered
Example
6. Restores accumulators and registers, CCR from stack (note: this includes restoring the I-bit of CCR)
7. Returns to instruction after the one that was interrupted
(note: other interrupts may be pending now)

17. Controlling Interrupts: The I-bit
General Info
Purpose/ Applications
Exists as bit 4 in the Condition Code Register (CCR)
When set (I=1), interrupts will be inhibited and placed as pending
When cleared (I=0), interrupt servicing will be allowed when asked
The I bit is always set while servicing an interrupt; Interrupts can’t nest
Set during RESET to allow minimum system initialization
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

18. Controlling Interrupts: The I-bit
General Info
Purpose/ Applications
Can also be set by software to prevent execution of maskable interrupts
SEI (SEt Interrupt Mask)
Can be cleared by software instructions
CLI (CLear Interrupt Mask)
Automatically cleared by RTI instruction
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

19. Maskable Interrupt: HPRIO
General Info
Purpose/ Applications
Can elevate the priority of one of the maskable interrupts.
Uses bits 0-3 of HPRIO (Highest PRIOrity Interrupt Register)
Default is IRQ.
Can be set at anytime during program as long as I bit is set.
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

20. Maskable Interrupt: IRQ
General Info
Purpose/ Applications
Highest priority maskable interrupt
IRQ pin provides additional external interrupting source
Other additional MCU pins can be used as interrupt inputs:
Example:
XIRQ input
Main-Timer Capture Pins
Pulse Accumulator Pin
IRQE Bit in the OPTION control used to specify IRQ pin configuration
IRQE = 0 -> Low level sensitive
IRQE = 1 -> Low-going edge sensitive (single source only)
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Example

21. Maskable Interrupt: IRQ
General Info
Purpose/ Applications
Controlled by a pin on the HC11
A low signal will initiate interrupt sequence
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts 1
Example

22. Non-maskable Interrupt: XIRQ
General Info
Purpose/ Applications
Enabled by TAP instruction by clearing X-bit upon system initialization
After being cleared, software cannot set the X-bit, thus XIRQ is non-maskable.
Higher priority than any source maskable by the I-bit.
Both the X and I bits are automatically set by hardware after stacking the CCR.
RTI restores X and I bit to pre-interrupt states
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Non-maskable interrupts
Example

23. Non-maskable Interrupt: SWI
General Info
Purpose/ Applications
Software instruction, thus cannot be interrupted until completed
Uninhibited by global mask bits in the CCR
Similar to other interrupts, sets the I-bit upon servicing
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
Non-maskable interrupts
Example

24. Example - IRQ handler General Info Purpose/ Applications
>>Whenever button is pushed, update a counter and print out the current count
Purpose/ Applications
1. Write the IRQ handler routine
IRQHANDLE ORG $3000
ldaa count ; A <-- current count inca ; increment count
staa count ; write back count
ldx #msg ; print out msg
jsr OUTSTRG
ldx #count ; print out count
jsr OUT1BYT
rti ; all done – return
org $2000 ; data section
msg fcc “Number of times button pressed:” fcb $04
count fcb 0 ; button counter
org $00ee
JMP IRQHANDLE
org $2200 ; main program
cli ; enable interrupts
loop bra loop ; endless loop
Interrupt Priority/ IVT
Controlling Interrupts
Maskable interrupts
2. Write the initialization and main routine
IRQ vector at $FFF2
Example
3. Do-nothing program!

25. The SIX untouchables: NONMASKABLE
RESET
CLOCK MONITOR
COP Watchdog
Illegal Opcode
XIRQ
SWI
Conclusion
Conclusion

26. Advantages and Disadvantages
Efficient, better than polling
Multitasking
Disadvantage
They can occur randomly
Requires additional hardware, sometimes
Conclusion
Conclusion

27. Questions?? General Info Purpose/ Applications Interrupt Priority/ IVT
Controlling Interrupts
Questions??
Maskable interrupts
Example
Conclusion

28. References
walker/Slides/Exceptions_Interrupts_1.ppt
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