1. Final Lecture Review Step 7 Deliverables Final Course Information

2. ECE Lab IV Lecture 92 Quiz 2 Opens Friday Aug. 22nd at 9am Closes Friday Aug 29 at 5pm Covers topics addressed in all parts of the voice recorder design including simulation, control circuitry, and specific chip performance (Hint, be sure you understand what it means to be edge triggered)

3. ECE Lab IV Lecture 93 Extended Lab Hours Eric will be available for extended lab hours starting this week. Week 9 and 10 Monday 12pm-4pm Wednesday 11am-5pm Friday 9am-4pm Finals Week Tuesday 12pm-4pm Wednesday 12pm-4pm Unless discussed with me otherwise all lab reports and disassembled boards are due Wednesday September 3rd by 4pm!!!!

4. ECE Lab IV Lecture 94 Step 7 Goals Control the ADC Modify the RAM control according to the chosen timing strategy Add the RAM chip to the circuit Optimize performance Test the circuit

6. ECE Lab IV Lecture 96 ADC Control ADC0804 Pins CS = Chip Select RD = Read WR = Write INTR = Interrupt 1 3 5 7 9 2 4 6 8 1011 13 15 17 19 12 14 16 18 20 CS RD WR CLK IN INTR DB0 DB7

7. ECE Lab IV Lecture 97 ADC Control Free-Running Circuit Rising transition on WR begins the conversion 100 ns min

8. ECE Lab IV Lecture 98 ADC Control Free-Running Circuit RD must be low for data to appear at outputs. When RD is high, outputs are Hi-Z.

9. ECE Lab IV Lecture 99 ADC Control Hint To avoid designing and wiring a lot of new logic, use the outputs and unused gates of your current RAM control as much as possible Verify ADC control on the logic analyzer BEFORE adding RAM chip to circuit

10. The first task is to make sure the 555 clock and the ADC internal clock are coordinated.

11. If WE_ never rises, no conversions will occur.

12. If there are no conversions, INTR_ will stay high.

13. There should be no pulses on WR_ in READ mode.

14. When RD_ is high the ADC output is high-impedance.

15. OE_ is low in READ mode.

16. ECE Lab IV Lecture 916 Optimizing the Circuit Goal: Record audio to your specs Storage is limited 131,072 sites in RAM (2 17 ) 65535 sites in RAM (2 16 ) Acquisition speed is limited ADC internal clock must make about 72 cycles per conversion High speed = high bandwidth High speed = short capture time

17. ECE Lab IV Lecture 917 Optimize the Circuit You have a design goal for how you want your circuit to function If necessary to meet this goal: Adjust the ADC internal clock frequency Adjust the on-board (555) clock

18. ECE Lab IV Lecture 918 Test the Circuit Display analog input (sine or ramp) and analog output on scope During the RAM WRITE cycle, the data on the bus comes from the ADC The DAC automatically converts it back to analog. At low frequencies, the DAC output should be identical to the analog input

19. ECE Lab IV Lecture 919 Test the Circuit Display analog input (sine or ramp) and analog output on scope During the RAM READ cycle, the data on the bus comes from the RAM The DAC automatically converts it back to analog The DAC output should be identical to the analog input of the previous acquisition cycle

20. ECE Lab IV Lecture 920 Test the Circuit Note the length of the acquisition (WRITE) cycle. Does it equal 131,072 times the period of the on-board clock? Note the length of the READ cycle. Does it equal 131,072 times the period of the on- board clock? If you want to see if the circuit is really working, pull the RAM chip Your output should be 0 during the READ cycle

21. ECE Lab IV Lecture 921 Experimental Results

22. ECE Lab IV Lecture 922 Deliverables Test 1 - Bandwidth Analog in, analog out Determine failure frequency A = (Goal - Measured)/Goal A ≤ 0 (measured exceeds goal) 20 pts 0.95 ≤ A < 1 18 pts 0.90 ≤ A < 0.95 16 pts A < 0.90 14 pts

23. ECE Lab IV Lecture 923 Deliverables Test 2 - Address Generator Working 17 bits20 pts Working 17 bits, novel design22 pts Working 16 bits16 pts < 16 bits10 pts

24. ECE Lab IV Lecture 924 Deliverables Test 3 - RAM/ADC Control Working and in sync20 pts Working not in sync15 pts Not working 10 pts

25. ECE Lab IV Lecture 925 Deliverables Test 4 - Timing ADC internal clock period INTR period 555 timer period Record time Playback time

26. ECE Lab IV Lecture 926 Deliverables Test 4 - Timing For record time: R = (Calculated - Measured)/Calculated If R ≥ 0.910 pts If R < 0.95 pts

27. ECE Lab IV Lecture 927 Deliverables Test 5 - Playback Is DAC output from stored data? Yes20 pts No10 pts

28. ECE Lab IV Lecture 928 Deliverables Test 6 - Construction Has the circuit been constructed neatly and with a reasonable floorplan? 0 to 10 pts

29. ECE Lab IV Lecture 929 Deliverables Test 7 - Understanding of Circuit Each group member will be asked questions to show that the entire group understands circuit operation and design choices and criteria

30. ECE Lab IV Lecture 930 Deliverables Test 8 - Return Board Has the circuit been returned in good condition? Good Conditionmultiplier = 1.0 Not Returnedmultiplier = 0.0

31. ECE Lab IV Lecture 931 Deliverables - Final Lab Report Write up your ADC control design: Design criteria what were the specs you wanted sketch the desired output waveforms Sketch the ADC control schematic Show any equations used, and define terms if necessary

32. ECE Lab IV Lecture 932 Deliverables- Final Lab Report Write up your ADC control design: Discuss what changes were made to the circuit to optimize performance How effective were they? Document the performance change

33. ECE Lab IV Lecture 933 Deliverables - Final Lab Report Have eric verify functionality and quality of work Comment on your observations and provide conclusions on the entire experiment Any improvements to this Step? Any improvement to the lab course?