1. Nov 29, 2006Dwingeloo, EVN CBD Meeting EVN D igital B ase B and C onverter Status Report Status Report G. Tuccari

2. Nov 29, 2006Dwingeloo, EVN CBD Meeting Digital Base Band Converter

3. Nov 29, 2006Dwingeloo, EVN CBD Meeting Digital Base Band Converter

4. Nov 29, 2006Dwingeloo, EVN CBD Meeting DBBC v.1.1 General Features 4 RF/IF Input from 16 in a range up to 2.200 GHz Four polarizations or bands available for a single group of 64 output data channel selection (2 VSI output connectors with at present 1 or 2 Gb/s each) 2 30,29 Hz or 512,1024 MHz sampling clock frequency each of the 4 sampler boards Channel bandwidth ranging between 250KHz and 16 MHz (MK4 modes), U&L or I&Q Channel bandwidth between 32 and 512 MHz (wide modes), I&Q Tuning step 1 Hz with 2 30,29 Hz sampling clock Multiple architecture using fully re-configurable FPGA Core Modules (Down- Converter, Equally Spaced Multichannel [even schematically called ‘polyphase filters’], DRx, etc.) Modular realization for cascaded stack processing

5. Nov 29, 2006Dwingeloo, EVN CBD Meeting DBBC ConditioningModule Pre-AD Conversion Signal Conditioning Pre-AD Conversion Signal Conditioning Pre-AD Conversion Nyquist Band Definition Pre-AD Conversion Nyquist Band Definition 4 RF Input Selection 4 RF Input Selection Output Level Control Output Level Control Total Power Mesurement Total Power Mesurement 2.2 GHz Bandwidth 2.2 GHz Bandwidth

6. Nov 29, 2006Dwingeloo, EVN CBD Meeting DBBC ADBoard Max Sampling clock single board: Max Sampling clock single board: 1.5 G Hz Output Data: 2 x 8-bit @ ¼ SClk DDR Output Data: 2 x 8-bit @ ¼ SClk DDR Analog to Digital Converter Analog to Digital Converter Analog input: 0 - 2.2 GHz Analog input: 0 - 2.2 GHz Max eq. Sampling clock interleaving four boards: 6.0 GHz Max eq. Sampling clock interleaving four boards: 6.0 GHz

7. Nov 29, 2006Dwingeloo, EVN CBD Meeting DBBC CoreBoard - Front Side Basic processing unit Basic processing unit Input Rate: Input Rate: (4 IFs x 2 bus x 8 bit x SClk/2) b/s (4 IFs x 2 bus x 8 bit x SClk/2) b/s Output Rate: Output Rate: (64 ch x 32-64-128) Mb/s (64 ch x 32-64-128) Mb/s Digital Down Converter: Digital Down Converter: 1 CoreModule = 1 BBC 1 CoreModule = 1 BBC Programmable architecture Programmable architecture Equally Spaced Multichannel: Equally Spaced Multichannel: 1 CoreModule = 64 real channels 1 CoreModule = 64 real channels 1 CoreModule = 32 complex channels 1 CoreModule = 32 complex channels

8. Nov 29, 2006Dwingeloo, EVN CBD Meeting DBBC FiLa Board First and Last board in the stack First and Last board in the stack First: First: Communication Interface Communication Interface JTAG programming channel JTAG programming channel 1PPS synchronizer 1PPS synchronizer Last: Last: 2 VSI Interfaces 2 VSI Interfaces DA Converter DA Converter

9. Nov 29, 2006Dwingeloo, EVN CBD Meeting DBBC 4 ADBoard + 8 CoreModule Stack

10. Nov 29, 2006Dwingeloo, EVN CBD Meeting Minimal Architecture With external RF control: 1 ADBoard 1 CoreBoard (down-converter, multichannel configuration, DRx) 1+1 FiLa board (VSI interface, DA converter, JTAG,etc.)

11. Nov 29, 2006Dwingeloo, EVN CBD Meeting Maximum Architecture 4 Conditioning Modules 1 FiLa board 4 ADBoard 16 CoreModule 1 FiLa board 1 CaT board PC Set PowerDistributor

12. Nov 29, 2006Dwingeloo, EVN CBD Meeting DBBC System v.1.1 on Nov 28, 2006 Down-converter system ready CaT (Clock and Timing) board added Configuration Firmware ready for most of the bandwidth Equi-spaced Multi-channel Firmware in test Testing in radiotelescopes is running Since Dec06 part of geo observations recorded in parallel to the std system for testing purposes

13. Nov 29, 2006Dwingeloo, EVN CBD Meeting DBBC v.2.0 System on Nov 29, 2006 Update program: -FPGA Virtex4 device for double processing clock (first prototype tested in August06, more boards under production) -FPGA Virtex5 engineer device waited for testing -Faster AD sampler with ADB2 for input bandwidth increasing (2.2GS/s, max bwd 3.5GHz), in collaboration with MPI (Michael Wunderlich) -FiLa10G under development in collaboration with with MPI (Michael Wunderlich) - RFI Mitigation Board: the first CoreBoard in the chain acts as RFI processor. Some test performed: a channel can be recovered if the RFI is not wide band and if the FFT bin span is small with respect to the channel span (about < 1/10). Astron interested in a joint development.

14. Nov 29, 2006Dwingeloo, EVN CBD Meeting ADB2

15. Nov 29, 2006Dwingeloo, EVN CBD Meeting FiLa10G Piggy-back board Triangle connection between HSI (DBBC fast sampled data bus) – 2xVSI – 10Gb link It can be placed either at the beginning of the chain or at the end The ADB2 is able to support FiLa10G for pure sampled data transmission The FiLa output board is able to support FiLa10G for processed data transmission It is a 2xVSI 10G converter DBBC output can be in parallel via 2xVSI and 10G Completion expected in mid-2007

16. Nov 29, 2006Dwingeloo, EVN CBD Meeting FiLa10G Connectivity 1ch HSI Max10bit Max 2.048GHz 2xVSI 64ch@128MHz 10G FiLa 10G 2 Optical Multimode Fibers (XPak Transceiver)

17. Nov 29, 2006Dwingeloo, EVN CBD Meeting DBBC Technology application to Digital Receiver L Band digital receiver under development in Effelsberg and Noto (in collaboration with Reinhard Keller et al.) DBBC parts are used with appropriate firmware for recording/transfering the sky frequency Recording on PCEVN (included in the receiver) Network data transfer with FiLa10G Software development for data processing, including entire band correlation A graduate thesis on this subject in IRA Noto is active A further thesis on this subject or 10G network development in spring 2007 in MPI Bonn A faster acquisition board development it’s necessary, with a data rate ≥ 2Gbps

18. Nov 29, 2006Dwingeloo, EVN CBD Meeting DBBC System on Nov 29, 2006 Observation of Aspiring stations in Evpatoria (Ukraine) and Irbene (Latvia), respectively in August and November a) A reduced version of DBBC run experiments in both stations b) PCEVN used to record such experiments in both 'pcevn format' and 'mk5 format‘ c) data saved on PCEVN disks and transferred in 'pcevn format' from the station to JIVE for software correlation d) data saved in 'mk5 format' and then later copied on the MK5A terminal for hardware correlation e) In Evpatoria fringes detected with Wb and Mc, problems with magnitude bit for encoding reasons f) Irbene test still under evaluation, no fringes at present with Tr and Nt, even in theNt-Tr baseline with not-standard receivers (12 GHz). Magnitude bit encoding fixed.

19. Nov 29, 2006Dwingeloo, EVN CBD Meeting DBBC Units production -IRA is at present taking care of the DBBC realization -Production of parts is realized by companies under IRA management -Multiwire and microwave PCB (CoreModule, FiLa, Conditioning, CaT) are realized in France by a specialized company -ADBoard realization: MPI -Boards are populated by an Italian company -Mechanical parts is done by an Italian company -Assembly, testing and validation in IRA -Three units ordered and under construction for Wettzel, Tigo, O’Higgins -MPI-Bonn required one unit -Russian Space Agency required three units -Even single boards available without any firmware for different applications (polarimeter, spectrometer, correlation, etc.) -Units today ordered are available after 3-6 months -A spin-of company is going to be set

20. Nov 29, 2006Dwingeloo, EVN CBD Meeting

21. Nov 29, 2006Dwingeloo, EVN CBD Meeting DBBC Cost Depends on the configuration Minimal architecture (1 ADB1 +1 CoreBoard + 2 FiLa+PowerDistributor): 6 K€ Complete system with 4 IF + 4 CoreBoard (1VSI 0.5-1 Gbps): 30 K€ Complete system with 4 IF + 8 CoreBoard (1VSI 1-2 Gbps): 45 K€ Complete system with 4 IF + 16 CoreBoard (2 VSI 1-4 Gbps each): 65 K€ Complete includes: PowerDistributor, PCSet, ConditioningModules, 19” Case & Power Supply