1. University of Tehran 1 Interface Design Transforms Omid Fatemi

2. University of Tehran 2 Transform “The output is like the input but different.”

3. University of Tehran 3 Typical Interface Design Connect ComputeConveyCooperate Sense Reality Touch Reality Connect Transform Embedded Systems Micros Assembler, C Real-Time Memory Peripherals Timers DMA PC interfaces HCI Busses Protocols Standards PCI IEEE488 SCSI USB & FireWire CAN

4. University of Tehran 4

5. University of Tehran 5 741 Circuit

6. University of Tehran 6 OPAMPs

7. University of Tehran 7 Operational Amplifier Circuits Inverting Amplifier Noninverting Amplifier V1V1 VoVo R1R1 R2R2 R3R3 V1V1 R1R1 R2R2 VoVo

8. University of Tehran 8 OPAMP MODELS Non-inverting Inverting

9. University of Tehran 9 Operational Amplifier Circuits Differential Amplifier Voltage Follower VoVo V1V1 R VoVo V1V1 R1R1 R2R2 R2R2 V2V2 R1R1

10. University of Tehran 10 Operational Amplifier Circuits Current to Voltage Converter Summing Amplifier R II VoVo VoVo V2V2 R2R2 R V3V3 R3R3 V1V1 R1R1

11. University of Tehran 11 Operational Amplifier Circuits Low-Pass Filter High-Pass Filter V1V1 VoVo R1R1 R2R2 R3R3 C R2R2 V1V1 VoVo R1R1 R3R3 C

12. University of Tehran 12 Operational Amplifier Circuits Comparator Comparator with Hysteresis V1V1 VoVo V ref 10Meg VoVo 10K V1V1 VsVs

13. University of Tehran 13 Instrumentation Amplifier

14. University of Tehran 14 Additional Op-Amp Circuits

15. University of Tehran 15 The Data Acquisition System Trans- ducer Analog Input Signal Cond. Analog Multiplexor Sample- and-Hold Other Analog Signals Multiplexer Address 2 Analog-to- Digital Converter N Digital Three- State Gates N Data To CPU End-of-Convert Start Convert

16. University of Tehran 16 Analog to Digital Conversion Main characteristics –Resolution –Dynamic range –Bandwidth –Conversion time Linearity –Integral –Differential Different types –Successive approximation –Slope integration –Flash Sigma Delta

17. University of Tehran 17 Analog to Digital Converter Analog input - Digital output –Most of the time commercial ASICs –Converts voltage or current What is to be converted? –Voltage, Current, Charge, Time Conditioning is required –To convert the measured quantity of a transducer –To adapt the impedances –To filter –To adapt the amplitude What is the expected resolution? What is the dynamic range? How often is a conversion needed?

18. University of Tehran 18 Resolution An ADC is given as an n-bit ADC The least significant bit gives the resolution of the ADC Related to full scale if the ADC is linear –LSB = A/2 n –Linear 8-bit ADC with a 1V full scale input –Resolution = 1/2 8 = 3.9 mV (0.39%) Dynamic range: –Ratio between the minimum and the maximum amplitude to be measured –an 8-bit ADC has a 256 dynamic range

19. University of Tehran 19 Conversion time and Bandwidth How often can a conversion be done –a few ns to a few ms depending on the technology »100 MHz FADC to slow sigma-delta Input bandwidth –Maximum input signal bandwidth »Track and hold input circuitry »Conversion frequency (FADC)

20. University of Tehran 20 ADC transfer curve Ideal ADC Errors –Offset –Integral non-linearity –Differential non-linearity

21. University of Tehran 21 Integral linearity Non linearity: maximum difference between the best linear fit and the ideal curve Non Linearity

22. University of Tehran 22 Differential non-linearity Least Significant Bit (LSB) value should be constant but it is not The difference with the ideal value shall not exceed 0.5 LSB

23. University of Tehran 23 Types of Conversion Errors

24. University of Tehran 24 Types of ADC Successive approximation Single slope integration Dual slope integration Flash ADC Sigma-Delta

25. University of Tehran 25 Successive Approximation A/D Compare the signal with an n-bit DAC output Change the code until –DAC output = ADC input An n-bit conversion requires n steps Requires a Start and an End signals Typical conversion time –1 to 50  s Typical resolution –8 to 12 bits MSBLSB D/A Converter Successive Approximation Register Ref Clock Analog Input Comparator Digital Outputs

26. University of Tehran 26 Single slope integration Start to charge a capacitor at constant current Count clock ticks during this time Stop when the capacitor voltage reaches the input Cannot reach high resolution –capacitor –comparator - + IN C R S Enable N-bit Output Q Oscillator Clk Counter Start Conversion Vin Counting time

27. University of Tehran 27 Dual slope integration (Wilkinson) Capacitor charged with a current proportional to the input during a fixed time Discharge at constant current Count of clock ticks during the discharge Typical resolution –10 to 18 bit Conversion time –Depends on the clock frequency Counting time Charge with a current proportional to the input

28. University of Tehran 28 Dual-slope A/D Integrator Output T 1 T 2 Fixed Time Measured Time Integrate Discharge Counter -Ref Clock Analog Input Comparator Digital Outputs Integrator C Control Logic R

29. University of Tehran 29 Flash ADC Direct measurement with 2 n -1 comparators Typical performance: –4 to 10-12 bits –15 to 300 MHz –High power Half-Flash ADC –2-step technique »1st flash conversion with 1/2 the precision »Subtracted with a DAC »New flash conversion Waveform digitizing applications

30. University of Tehran 30 Flash A/D Ref Analog Input 2 N - 1 Comparators Digital Outputs Decoder R 2R R

31. University of Tehran 31 Flash ADC (cont) Pipeline ADC Input-to-output delay = n clocks for n stages One output every clock cycle Saves power (less comparators) S&H 3-bit FADC3-bit DAC - X 4 3-bit S&HStage 1Stage 2Stage 3Stage 44-bit FADC Time Adjustment & Digital Error Correction 3-bit 4-bit 12-bit Input

32. University of Tehran 32 Sigma-Delta ADC Very low resolution (1-bit) Very high sampling rate (MHz) Usually over-sampled. Digital filters –The resolution can be increased to as many as 20 or more bits. Useful for high resolution conversion of low-frequency signals 1-bit ADC 1-bit DAC - Input Output 1rst Order Sigma-Delta Modulator

33. University of Tehran 33 Resolution/Throughput Rate

34. University of Tehran 34 Tracking A/D MSBLSB D/A Converter Up/Down Counter Ref Clock Analog Input Comparator Digital Outputs UP DOWN Track/ Hold

35. University of Tehran 35 Quantization Process

36. University of Tehran 36 Quantization Error  (x) q An n bit ADC introduces a quantization error Encoding a signal (A/2) sin  t with A being the full scale will give an error Signal to Noise Ratio

37. University of Tehran 37 Shannon Theorem A signal x(t) has a spectral representation |X(f)|; X(f) = Fourier transform of x(t) A signal x(t) after having been digitised at the frequency f s, has a spectral representation equal to the spectral representation of x(t) shifted every f s If X(f) is not equal to zero when f > f s /2, there is spectrum overlapping The Shannon theorem says that x(t) can be reconstructed after digitization if the digitizing frequency is at least twice the maximum frequency in x(t) spectral representation This is mathematical only, as it supposes perfect filtering

38. University of Tehran 38 Example (1) “Typical” physics pulse –100 ns rising and falling edge Effect of a digitisation at 10 MHz and 20 MHz

39. University of Tehran 39 Example (2) 100 ns square pulse Digitisation at 10 MHz and 20 MHz

40. University of Tehran 40 At Twice the Frequency

41. University of Tehran 41 Above Nyquest

42. University of Tehran 42 D/A Conversion Desired Sinusoid D/A Output N / Data Latch N / Data D-to-A Converter Signal Conditioner Analog Output Latch Enable Common Types Binary Weighted D/A R/2R Ladder Network D/A

43. University of Tehran 43 Binary Weighted D/A Analog Output B0B0 B1B1 B2B2 B3B3 Ref. V 100K 50K 25K 12.5K 6.25K Must have a wide range of resistors

44. University of Tehran 44 R-2R Ladder D/A Analog Output B0B0 B1B1 B2B2 B3B3 Ref. V 2R 2R 2R R R Wide range of resistors not required

45. University of Tehran 45 R-2R Analysis

46. University of Tehran 46 D/A Converter Specifications Resolution and linearity –Determined by the number of bits »given by the voltage corresponding to the smallest step. –Linearity shows how closely the output voltage follows a straight line between 0 and V max Settling time –Time to settle within ± ½ LSB Glitches –Caused by a differing switch speeds »e.g. 1000000  01111111 could yield 00000000

47. University of Tehran 47 Other Analog I/O Methods Voltage-to-frequency converters (VCO) Pulse-width modulated analog output VCO Counter Analog Input f N T t A By lp filtering Average = At/T

48. University of Tehran 48 Selecting an A/D Converter The requirement is to read a temperature sensor which will range from -200 degrees Celcius to +50 degrees with an accuracy of 0.1 degree. What is the required number of bits for the A/D converter? Will the 68HC812A4 (has 8 8-bit ADC) microcontroller work?

49. University of Tehran 49 Calculations for A/D find out how many different values are required: –-200.0 to 50.0 inclusive is 2502 different values –2 11 is 2048 different values –2 12 is 4096 different values so this would be the minimum number of bits 68HC812A4 has eight channels of 8 bit A/D so it would need an external A/D chip.

50. University of Tehran 50 Summary OP-AMPs OP Amp circuits Analog to digital converters Quantization Sampling frequency Digital to analog converters