1. Caching & Virtual Memory Systems Chapter 7  Caching l To address bottleneck between CPU and Memory l Direct l Associative l Set Associate  Virtual Memory Systems l To address bottleneck between Memory & Disk l Organization l Page faults l Lookaside Buffer Simplicity is the goal, but it is hard work to keep it simple!

2. Direct Mapped Caching

3. Direct Mapping Caching

4. Direct Mapping Cache with Larger Blocks

5. Associative Mapped Caching  Direct mapped caching allows any given main memory block to be mapped into one unique cache location.  Associative mapped caching allows any given main memory block to be mapped into any cache location. How does the length of the tag for Associative compare with that for Direct?

6. Set Associative Caching

7. Four-Way Set Associative Cache  2 8 = 256 sets each with four ways (each with one block) 31 30... 13 12 11... 2 1 0 Byte offset Data TagV 0 1 2. 253 254 255 Data TagV 0 1 2. 253 254 255 Data TagV 0 1 2. 253 254 255 Index Data TagV 0 1 2. 253 254 255 8 Index 22 Tag HitData 32 4x1 select

8. Direct vs Associate Caching Memory Organizations

9. Range of Set Associative Caches  For a fixed size cache, each increase by a factor of two in associativity doubles the number of blocks per set (i.e., the number or ways) and halves the number of sets – decreases the size of the index by 1 bit and increases the size of the tag by 1 bit Block offsetByte offsetIndexTag

10. Range of Set Associative Caches  For a fixed size cache, each increase by a factor of two in associativity doubles the number of blocks per set (i.e., the number or ways) and halves the number of sets – decreases the size of the index by 1 bit and increases the size of the tag by 1 bit Block offsetByte offsetIndexTag Decreasing associativity Fully associative (only one set) Tag is all the bits except block and byte offset Direct mapped (only one way) Smaller tags Increasing associativity Selects the setUsed for tag compareSelects the word in the block

11. Costs of Set Associative Caches  When a miss occurs, which block do we pick for replacement? l Least Recently Used (LRU): the block replaced is the one that has been unused for the longest time -Must have hardware to keep track of when each way’s block was used relative to the other blocks in the set -For 2-way set associative, takes one bit per set → set the bit when a block is referenced (and reset the other way’s bit)  N-way set associative cache costs l N comparators (delay and area) l MUX delay (set selection) before data is available l Data available after set selection (and Hit/Miss decision). In a direct mapped cache, the cache block is available before the Hit/Miss decision -So its not possible to just assume a hit and continue and recover later if it was a miss

12. Benefits of Set Associative Caches  The choice of direct mapped or set associative depends on the cost of a miss versus the cost of implementation Data from Hennessy & Patterson, Computer Architecture, 2003  Largest gains are in going from direct mapped to 2-way (20%+ reduction in miss rate) Note: Figure 7.30 in your text does not seems to be very different.

13. Another graph on Associativity

14. Multiple Caches  Virtually all modern computers employ caching  In fact, they employ multiple caches. Why?  But there organizations (organization, associativity, size) differ  “In most cases”, they follow a memory pyramid

15. Pentium 4 Block Diagram

16. PowerPC G5 Block Diagram

17. Key Cache Design Parameters L1 typicalL2 typical Total size (blocks)250 to 2000 4000 to 250,000 Total size (KB)16 to 64500 to 8000 Block size (B)32 to 6432 to 128 Miss penalty (clocks)10 to 25100 to 1000 Miss rates (global for L2) 2% to 5%0.1% to 2%

18. Two Machines’ Cache Parameters Intel P4AMD Opteron L1 organizationSplit I$ and D$ L1 cache size8KB for D$, 96KB for trace cache (~I$) 64KB for each of I$ and D$ L1 block size64 bytes L1 associativity4-way set assoc.2-way set assoc. L1 replacement~ LRULRU L1 write policywrite-throughwrite-back L2 organizationUnified L2 cache size512KB1024KB (1MB) L2 block size128 bytes64 bytes L2 associativity8-way set assoc.16-way set assoc. L2 replacement~LRU L2 write policywrite-back

19. Summary: The Cache Design Space  Several interacting dimensions l cache size l block size l associativity l replacement policy l write-through vs write-back  The optimal choice is a compromise l depends on access characteristics -workload -use (I-cache, D-cache, TLB) l depends on technology / cost  Simplicity often wins Associativity Cache Size Block Size

20. Summary: What happens on a Cache write?  Write-through – The information is written to both the block in the cache and to the block in the next lower level of the memory hierarchy l Write-through is always combined with a write buffer so write waits to lower level memory can be eliminated (as long as the write buffer doesn’t fill)  Write-back – The information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced. l Need a dirty bit to keep track of whether the block is clean or dirty  Pros and cons of each? l Write-through: read misses don’t result in writes (so are simpler and cheaper) l Write-back: repeated writes require only one write to lower level Processor Cache DRAM

21. Improving Cache Performance  Reduce the time to hit in the cache l smaller cache l direct mapped cache l smaller blocks l for writes -Write-through -Write-back  Reduce the miss rate l bigger cache l more flexible placement (increase associativity) l larger blocks (16 to 64 bytes typical) l Use “victim cache” – small buffer holding most recently discarded blocks

22. Improving Cache Performance  Reduce the miss penalty l smaller blocks l use a write buffer to hold dirty blocks being replaced so don’t have to wait for the write to complete before reading l check write buffer (and/or victim cache) on read miss – may get lucky l for large blocks fetch critical word first l use multiple cache levels – L2 cache not tied to CPU clock rate l faster backing store/improved memory bandwidth -wider buses -memory interleaving, page mode DRAMs

23. Virtual Memory System To address bottleneck between Memory & Disk l Discussing the problem l Organization l Page faults l Lookaside Buffer

24. Back to The Memory Hierarchy Increasing distance from the processor in access time L1$ L2$ Main Memory Secondary Memory Processor (Relative) size of the memory at each level Inclusive– what is in L1$ is a subset of what is in L2$ is a subset of what is in MM that is a subset of is in SM 4-8 bytes (word) 1 to 4 blocks 1,024+ bytes (disk sector = page) 8-32 bytes (block)  Take advantage of the principle of locality to present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technology

25. Virtual Memory System vs Caching  Caching is essentially a architecture / hardware problem  Virtual memory Systems are an Operating System problem with a requirement for architecture / hardware support  Why?

26. Recall Memory Differences TechnologyAccess TimeCost/GB SRAM 0.5 – 5 ns $4,000 - $10,000 DRAM 50 – 70 ns $100 - $200 Disk 5 – 20 ms $0.50 - $2 DRAM access 40 times SRAM access Disk access 1,000,000 times DRAM access Note: Block reads/writes can be done much faster (maybe 1000 times)

27. Virtual Memory  Use main memory as a “cache” for secondary memory l Allows efficient and safe sharing of memory among multiple programs l Provides the ability to easily run programs larger than the size of physical memory l Simplifies loading a program for execution by providing for code relocation (i.e., the code can be loaded anywhere in main memory)  What makes it work? – again the Principle of Locality l A program is likely to access a relatively small portion of its address space during any period of time  Each program is compiled into its own address space – a “virtual” address space l During run-time each virtual address must be translated to a physical address (an address in main memory)

28. Two Programs Sharing Physical Memory Program 1 virtual address space main memory  A program’s address space is divided into pages (all one fixed size) or segments (variable sizes) l The starting location of each page (either in main memory or in secondary memory) is contained in the program’s page table Program 2 virtual address space

29. Address Translation Virtual Address (VA) Page offsetVirtual page number 31 30... 12 11... 0 Page offsetPhysical page number Physical Address (PA) 29... 12 11 0 Translation  So each memory request first requires an address translation from the virtual space to the physical space l A virtual memory miss (i.e., when the page is not in physical memory) is called a page fault  A virtual address is translated to a physical address by a combination of hardware and software

30. Address Translation Mechanisms Physical page base addr Main memory Disk storage Virtual page # V 1111110101011111101010 Page Table (in main memory) Offset Physical page # Offset

31. Virtual Paging

32. Virtual Addressing with a Cache  It takes an extra memory access to translate a VA to a PA CPU Trans- lation Cache Main Memory VAPA miss hit data  This makes memory (cache) accesses very expensive (if every access was really two accesses)  The hardware fix is to use a Translation Lookaside Buffer (TLB) – a small cache that keeps track of recently used address mappings to avoid having to do a page table lookup

33. Making Address Translation Fast Physical page base addr Main memory Disk storage Virtual page # V 1111110101011111101010 1110111101 Tag Physical page base addr V TLB Page Table (in physical memory)

34. Virtual Addressing with Look Ahead Buffer Intrinsity Design

35. Translation Lookaside Buffers (TLBs)  Just like any other cache, the TLB can be organized as fully associative, set associative, or direct mapped V Virtual Page # Physical Page # Dirty Ref Access  TLB access time is typically smaller than cache access time (because TLBs are much smaller than caches) l TLBs are typically not more than 128 to 256 entries even on high end machines

36. A TLB in the Memory Hierarchy  A TLB miss – is it a page fault or merely a TLB miss? l If the page is loaded into main memory, then the TLB miss can be handled (in hardware or software) by loading the translation information from the page table into the TLB -Takes 10’s of cycles to find and load the translation info into the TLB l If the page is not in main memory, then it’s a true page fault -Takes 1,000,000’s of cycles to service a page fault  TLB misses are much more frequent than true page faults CPU TLB Lookup Cache Main Memory VAPA miss hit data Trans- lation hit miss ¾ t ¼ t

37. Some Virtual Memory Design Parameters Paged VMTLBs Total size16,000 to 250,000 words 16 to 512 entries Block size1000 to 16,0001 to 8 Miss penalty (clocks)10,000,000 to 100,000,000 10 to 1000 Miss rates0.00001% to 0.0001% 0.01% to 2%

38. Two Machines’ Cache Parameters Intel P4AMD Opteron TLB organization1 TLB for instructions and 1 TLB for data Both 4-way set associative Both use ~LRU replacement Both have 128 entries TLB misses handled in hardware 2 TLBs for instructions and 2 TLBs for data Both L1 TLBs fully associative with ~LRU replacement Both L2 TLBs are 4-way set associative with round-robin LRU Both L1 TLBs have 40 entries Both L2 TLBs have 512 entries TBL misses handled in hardware

39. TLB Event Combinations TLBPage Table CachePossible? Under what circumstances? Hit Miss Hit MissHitMiss HitMissMiss/ Hit Miss Hit

40. TLB Event Combinations TLBPage Table CachePossible? Under what circumstances? Hit Miss Hit MissHitMiss HitMissMiss/ Hit Miss Hit Yes – what we want! Yes – although the page table is not checked if the TLB hits Yes – TLB miss, PA in page table Yes – TLB miss, PA in page table, but data not in cache Yes – page fault Impossible – TLB translation not possible if page is not present in memory Impossible – data not allowed in cache if page is not in memory

41. The Hardware/Software Boundary  What parts of the virtual to physical address translation is done by or assisted by the hardware? l Translation Lookaside Buffer (TLB) that caches the recent translations -TLB access time is part of the cache hit time -May allot an extra stage in the pipeline for TLB access l Page table storage, fault detection and updating -Page faults result in interrupts that are then handled by the OS -Hardware must support (i.e., update appropriately) Dirty and Reference bits (e.g., ~LRU) in the Page Tables l Disk placement -Bootstrap (e.g., out of disk sector 0) so the system can service a limited number of page faults before the OS is even loaded

42. Summary  The Principle of Locality: l Program likely to access a relatively small portion of the address space at any instant of time. -Temporal Locality: Locality in Time -Spatial Locality: Locality in Space  Caches, TLBs, Virtual Memory all understood by examining how they deal with the four questions 1. Where can block be placed? 2. How is block found? 3. What block is replaced on miss? 4. How are writes handled?  Page tables map virtual address to physical address l TLBs are important for fast translation

43. Next class  Talk about the IA 64 Processor Superscaler Processor