1. Updated Interconnect Proposal Bob Ross, Teraspeed Labs bob@teraspeedlabs.com EPEPS 2015 IBIS Summit San Jose, CA, October 28, 2015 Updated Interconnect Proposal Bob Ross, Teraspeed Labs bob@teraspeedlabs.com EPEPS 2015 IBIS Summit San Jose, CA, October 28, 2015 Draft Presented September 2, 2015 at the Interconnect Working Group Copyright 2015 Teraspeed Labs 1

2. Goal Give an update to Interconnect proposal Terminal section 2 Copyright 2015 Teraspeed Labs

3. Reference Example 3 Copyright 2015 Teraspeed Labs pin_names signal_names for POWER/GND pins pad_names for implicitly shorted pads or on-die shorted connections for POWER/GND pins

4. Partial Reference Diagram (A3, D1, D2 Omitted) 4 Copyright 2015 Teraspeed Labs Physical Buffer, its Model and On-Die Interconnect PadsPins A1 P1 P2 P3 P4 P5 G1 G2 G3 G4 G5 A2 Die A1 A2 Pdref(A2) Puref(A2) Pdref(A1) Puref(A1) IBIS Buffer Models

5. Terminal Syntax 5 Copyright 2015 Teraspeed Labs [Begin Interconnect Model] …| Other syntax Number_of_terminals = | List follows …| More lines … [End Interconnect Model] ___________________________________________________________________ : pin_name, signal_name from [Pin] keyword, or pad_name from [Pin Mapping] keyword Convention: “shorted” connection electrical connection

6. Legal Interconnection Terminals 6 Copyright 2015 Teraspeed Labs Terminal_Typepin_namesignal_namepad_nameAggressor Buffer_I/O X Z Puref X Pdref X Pcref X Gcref X Extref X Buffer_rail YY Pad_I/O X Pad_rail YYY Pin_I/O X Pin_rail YY X: I/O pin_names, Y: POWER/GND names, Z: Optional Aggressor

7. Reference Example 7 Copyright 2015 Teraspeed Labs pin_names signal_names for POWER/GND pins pad_names for implicitly shorted pads or on-die shorted connections for POWER/GND pins

8. With pad_name = signal_name 8 Copyright 2015 Teraspeed Labs pin_names signal_names for POWER/GND pins pad_names for implicitly shorted pads or on-die shorted connections for POWER/GND pins New Pad_signal_name subparameter indicates that POWER/GND pins do not have to be listed

9. Pin-to-Buffer Interconnect Example using pin_names only 9 Copyright 2015 Teraspeed Labs [Pin Mapping] not needed, all connections are pin-to-buffer (Similar to [Package] model direct connection to I/O buffer)

10. Pin-to-Buffer Interconnect Example 10 Copyright 2015 Teraspeed Labs Physical Buffer, its Model and On-Die Interconnect PadsPins A1 P1 P2 P3 P4 P5 G1 G2 G3 G4 G5 A2 Die A1 A2 Pdref(A2) Puref(A2) Pdref(A1) Puref(A1)

11. Power Rails Interconnect Example with signal_name 11 Copyright 2015 Teraspeed Labs [Pin Mapping] optional if bus_names are signal_names

12. Pin-to-Buffer Interconnect Example with signal_name 12 Copyright 2015 Teraspeed Labs Physical Buffer, its Model and On-Die Interconnect PadsPins A1 P1 P2 P3 P4 P5 G1 G2 G3 G4 G5 A2 Die A1 A2 Pdref(A2) Puref(A2) Pdref(A1) Puref(A1) VDD VSS

13. Example with pad_name Groups 13 Copyright 2015 Teraspeed Labs pin_names signal_names for POWER/GND pins pad_names for implicitly shorted pads or on-die shorted connections for POWER/GND pins

14. Power Rails Interconnect Example with signal_name and pad_names 14 Copyright 2015 Teraspeed Labs

15. Pin-to-Buffer Interconnect Example with signal_name and pad_names 15 Copyright 2015 Teraspeed Labs Physical Buffer, its Model and On-Die Interconnect PadsPins A1 P1 P2 P3 P4 P5 G1 G2 G3 G4 G5 A2 Die A1 A2 Pdref(A2) Puref(A2) Pdref(A1) Puref(A1) VDD VSS VDD1 VDD2 VDD3 VSS1 VSS2 VSS3

16. Default “shorted” Interconnect with [Pin Mapping] 16 Copyright 2015 Teraspeed Labs Physical Buffer, its Model and On-Die Interconnect PadsPins A1 P1 P2 P3 P4 P5 G1 G2 G3 G4 G5 A2 Die A1 A2 Pdref(A2) Puref(A2) Pdref(A1) Puref(A1) VDD VSS VDD1 VDD2 VDD3 VSS1 VSS2 VSS3

17. Conclusion and Issues Table has been revised o Added pin connection for pad pin_name o Used Y for all POWER/GND, Z for Aggressor column How to handle several Interconnect Models that are supposed to be used together 17 Copyright 2015 Teraspeed Labs