1. Lecture 1: Introduction
Original Lecture notes © 2010 David Money Harris
Modified by Konstantinos Tatas

2. ACOE419 – Digital IC and VLSI Design
ECTS: 5
Conduct hours per week: 3 (2 Lecture – 1 Lab)
Evaluation:
Final Exam: 60%
Laboratory exercises: 20%
Test: 10%
Assignment: 10%
1: Introduction

3. Course outline and breakdown
Week 1:
Introduction to VLSI Design
Week 2:
Stick diagrams and layout
Lab 1: Basic schematic entry
Week 3:
The ideal MOS transistor
Lab 2: Compound gates
Week 4:
The non-ideal MOS transistor
Lab3: Basic Layout
1: Introduction

4. Course outline and breakdown
Week 5:
Logical Effort
Lab 4: Advanced Layout
Week 6:
Power Consumption
Lab 5: MOS transistor characteristics
Week 7:
Test
Lab 6: Logical Effort
Week 8:
Simulation
Lab 7: Power Consumption
1: Introduction

5. Course outline and breakdown
Week 9:
Combinational Circuit Design
Lab 8: Power Consumption
Week 10:
Wires
Lab 9: Combinational Circuit Design
Week 11:
Sequential Circuit Design
Lab 10
Week 12:
Adder Design
Lab 11
1: Introduction

6. Introduction Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): bucketloads!
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
Today: How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip
1: Introduction

7. Courtesy Texas Instruments
A Brief History
1958: First integrated circuit
Flip-flop using two transistors
Built by Jack Kilby at Texas Instruments
2010
Intel Core i7 mprocessor
2.3 billion transistors
64 Gb Flash memory
> 16 billion transistors
Courtesy Texas Instruments
[Trinh09]
© 2009 IEEE.
1: Introduction

8. Growth Rate 53% compound annual growth rate over 50 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society
[Moore65]
Electronics Magazine
1: Introduction

9. Annual Sales >1019 transistors manufactured in 2008
1 billion for every human on the planet
1: Introduction

10. Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable
1947: first point contact transistor
John Bardeen and Walter Brattain at Bell Labs
See Crystal Fire
by Riordan, Hoddeson
AT&T Archives. Reprinted with permission.
1: Introduction

11. Transistor Types Bipolar transistors npn or pnp silicon structure
Small current into very thin base layer controls large currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between source and drain
Low power allows very high integration
1: Introduction

12. MOS Integrated Circuits
1970’s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
Intel Museum.
Reprinted with permission.
[Vadasz69]
© 1969 IEEE.
Intel bit SRAM
Intel bit mProc
1: Introduction

13. Moore’s Law: Then 1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI: 10 gates
MSI: gates
LSI: 10,000 gates
VLSI: > 10k gates
[Moore65]
Electronics Magazine
1: Introduction

14. And Now…
1: Introduction

15. Feature Size Minimum feature size shrinking 30% every 2-3 years
1: Introduction

16. Corollaries Many other factors grow exponentially
Ex: clock frequency, processor performance
1: Introduction

17. Silicon Lattice Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
1: Introduction

18. Dopants Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
1: Introduction

19. p-n Junctions
A junction between p-type and n-type semiconductor forms a diode.
Current flows only in one direction
1: Introduction

20. nMOS Transistor Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal – oxide – semiconductor (MOS) capacitor
Even though gate is
no longer made of metal
1: Introduction

21. nMOS Operation Body is usually tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
1: Introduction

22. nMOS Operation Cont. When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from source through channel to drain, transistor is ON
1: Introduction

23. pMOS Transistor Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
1: Introduction

24. Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
1: Introduction

25. Transistors as Switches
We can view MOS transistors as electrically controlled switches
Voltage at gate controls path from source to drain
1: Introduction

26. CMOS Inverter A Y 1
OFF ON 1 ON
OFF
1: Introduction

27. CMOS NAND Gate A B Y 1 OFF ON 1 OFF ON 1 ON OFF ON OFF 11
OFF ON 1
OFF ON 1 ON
OFF ON
OFF 1
1: Introduction

28. CMOS NOR Gate A B Y 1
1: Introduction

29. 3-input NAND Gate Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
1: Introduction

30. Example
Sketch a 3-input CMOS NOR gate
1: Introduction

31. Complementary CMOS Complementary CMOS logic gates
nMOS pull-down network
pMOS pull-up network
a.k.a. static CMOS
Pull-up OFF
Pull-up ON
Pull-down OFF
Z (float) 1
Pull-down ON
X (crowbar)
1: Introduction

32. Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON
Parallel: either can be ON
1: Introduction

33. Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Requires parallel pMOS
Rule of Conduction Complements
Pull-up network is complement of pull-down
Parallel -> series, series -> parallel
1: Introduction

34. Compound Gates Compound gates can do any inverting function Ex:
1: Introduction

35. Example: O3AI
1: Introduction

36. Example
Sketch a transistor-level schematic for a single-stage CMOS logic gate for each of the following functions:
(ABC+D)΄
((AB+C)D)΄
(AB+(C(A+B)))΄
1: Introduction

37. Signal Strength Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
But degraded or weak 1
pMOS pass strong 1
But degraded or weak 0
Thus nMOS are best for pull-down network
1: Introduction

38. Pass Transistors
Transistors can be used as switches
1: Introduction

39. Transmission Gates Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
1: Introduction

40. Tristates Tristate buffer produces Z when not enabled EN A Y Z 1Z 1
1: Introduction

41. Nonrestoring Tristate
Transmission gate acts as tristate buffer
Only two transistors
But nonrestoring
Noise on A is passed on to Y
1: Introduction

42. Tristate Inverter Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
1: Introduction

43. Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y X 1X 1
1: Introduction

44. Gate-Level Mux Design How many transistors are needed? 20
1: Introduction

45. Transmission Gate Mux Nonrestoring mux uses two transmission gates
Only 4 transistors
1: Introduction

46. Inverting Mux Inverting multiplexer Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
Noninverting multiplexer adds an inverter
1: Introduction

47. 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects
Two levels of 2:1 muxes
Or four tristates
1: Introduction

48. D Latch When CLK = 1, latch is transparent
D flows through to Q like a buffer
When CLK = 0, the latch is opaque
Q holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch
1: Introduction

49. D Latch Design
Multiplexer chooses D or old Q
1: Introduction

50. D Latch Operation
1: Introduction

51. D Flip-flop When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, master-slave flip-flop
1: Introduction

52. D Flip-flop Design Built from master and slave D latches
1: Introduction

53. D Flip-flop Operation
1: Introduction

54. Race Condition Back-to-back flops can malfunction from clock skew
Second flip-flop fires late
Sees first flip-flop change and captures its result
Called hold-time failure or race condition
1: Introduction

55. Nonoverlapping Clocks
Nonoverlapping clocks can prevent races
As long as nonoverlap exceeds clock skew
We will use them in this class for safe design
Industry manages skew more carefully instead
1: Introduction

56. CMOS Fabrication CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or etched
Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
1: Introduction

57. Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
1: Introduction

58. Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
1: Introduction

59. Inverter Mask Set Transistors and wires are defined by masks
Cross-section taken along dashed line
1: Introduction

60. Detailed Mask Views Six masks n-well Polysilicon n+ diffusion
p+ diffusion
Contact
Metal
1: Introduction

61. Fabrication Chips are built in huge factories called fabs
Contain clean rooms as large as football fields
Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
1: Introduction

62. Fabrication Steps Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
1: Introduction

63. Oxidation Grow SiO2 on top of Si wafer
900 – 1200 C with H2O or O2 in oxidation furnace
1: Introduction

64. Photoresist Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
1: Introduction

65. Lithography Expose photoresist through n-well mask
Strip off exposed photoresist
1: Introduction

66. Etch Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
1: Introduction

67. Strip Photoresist Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step
1: Introduction

68. n-well n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
1: Introduction

69. Strip Oxide Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
1: Introduction

70. Polysilicon Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
1: Introduction

71. Polysilicon Patterning
Use same lithography process to pattern polysilicon
1: Introduction

72. Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well contact
1: Introduction

73. N-diffusion Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing
1: Introduction

74. N-diffusion cont. Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
1: Introduction

75. N-diffusion cont. Strip off oxide to complete patterning step
1: Introduction

76. P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
1: Introduction

77. Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
1: Introduction

78. Metalization Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
1: Introduction

79. Layout Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design rules
Express rules in terms of l = f/2
E.g. l = 0.3 mm in 0.6 mm process
1: Introduction

80. Simplified Design Rules
Conservative rules to get you started
1: Introduction

81. Inverter Layout Transistor dimensions specified as Width / Length
Minimum size is 4l / 2l, sometimes called 1 unit
In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
1: Introduction

82. Gate Layout Layout can be very time consuming
Design gates to fit together nicely
Build a library of standard cells
Standard cell design methodology
VDD and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
1: Introduction

83. Example: Inverter
1: Introduction

84. Example: NAND3 Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32 l by 40 l
1: Introduction

85. Stick Diagrams Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers
1: Introduction

86. Wiring Tracks A wiring track is the space required for a wire
4 l width, 4 l spacing from neighbor = 8 l pitch
Transistors also consume one wiring track
1: Introduction

87. Well spacing Wells must surround transistors by 6 l
Implies 12 l between opposite transistor flavors
Leaves room for one wire track
1: Introduction

88. Area Estimation Estimate area by counting wiring tracks
Multiply by 8 to express in l
1: Introduction

89. Example: O3AI Sketch a stick diagram for O3AI and estimate area
1: Introduction

90. Example
Draw a stick diagram and estimate the area for a 4-input NOR gate
1: Introduction

91. Example
For a compound gate implementing the boolean function F=((A+B)C)΄:
Sketch a transistor-level schematic
Sketch a stick diagram
Estimate the area from the stick diagram
1: Introduction

92. Summary MOS transistors are stacks of gate, oxide, silicon
Act as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start designing schematics and layout for a simple chip!
1: Introduction

93. Spice netlist vdd vdd gnd 5
Vin a gnd pwl 0ps 0 10ns ns 5 50ns ns 0
*** TOP LEVEL CELL: myinv2{lay}
y a gnd gnd N L=0.8U W=0.8U AS=3.54P AD=1.72P PS=8.15U PD=5.8U
vdd a y vdd P L=0.8U W=1.6U AS=5.2P AD=3.54P PS=9.7U PD=8.15U
1: Introduction