1. 2004 MAPLD, Paper 190 JJ Wang 1 SEU-Hardened Storage Devices in a 0.15 µm Antifuse FPGA – RTAX-S J. J. Wang 1, B. Cronquist 1, J. McCollum 1, R. Gorgis 1, R. Katz 2, and I. Kleyner 3 1 Actel Corporation 2 NASA Office of Logic Design 3 Orbital Science, Greenbelt, MD20771

2. 2004 MAPLD, Paper 190 JJ Wang 2 Abstract The storage devices in the RTAX-S family are SEU-hardened. The flip-flop is hardened by hard- wired triple module redundancy, and the RAM is hardened by software error-correcting code (ECC), which is a shortened Hamming code. These hardened storage devices are tested by heavy ion beam, and their SEU cross sections are extracted from test data for rate predictions in a typical environment. Final results show that both devices are hardened effectively, and the measured upset errors are due to SET and noise.

3. 2004 MAPLD, Paper 190 JJ Wang 3 Triple Module Redundant Flip-Flop (K-Latch)

4. 2004 MAPLD, Paper 190 JJ Wang 4 TMR Flip-Flop Heavy Ion Beam Test Device under test: RTAX2000-S Four pre-production devices Logic design: Two 100-bit shift registers, SH1 and SH2, for SEU measurement Two user-level TMR shift registers for noise monitoring Checkerboard pattern running at 2 MHz during irradiation -10% V CC for SEU measurement, +10% V CC for SEL and SEDR Heavy ion beam: BNL Tandem Van de Graaff Cl-35, Ni-58, Br-81, I-127 Effective LET=37.5 to 104 MeVcm 2 /mg

5. 2004 MAPLD, Paper 190 JJ Wang 5 Hard-wired TMR Flip-Flop Cross Section per bit Weibull Fit

6. 2004 MAPLD, Paper 190 JJ Wang 6 TMR Flip-Flop SEU Rate Prediction Use Space Radiation 4.5 simulator: Weibull parameters: LET 0 =10MeVcm 2 /mg, width=35MeVcm 2 /mg, shape=2, saturation cross-section=9x10 -10 cm 2 Active volume: depth=0.15µm, funnel depth=0.3µm Environment: GEO solar minimum Shielding: 100mil Aluminum Upsets Rate: 1.96x10 -11 upsets/bitday Based on RTSX-S experiences, the measured upsets are probably due to SET and testing noise

7. 2004 MAPLD, Paper 190 JJ Wang 7 EDAC-RAM in RTAX-S ECC: Shortened Hamming code to detect 2 errors and correct 1 error S. Lin and D. J. Cosello, Jr., “Error Control Coding: Fundamentals and Applications,” Prentice Hall, New Jersey, 1983 http://www.actel.com/documents/EDAC_AN.pdfhttp://www.actel.com/documents/EDAC_AN.pdf “Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs” Scrubbing: Reduce SEU rate for long-term storage User selects the scrubbing rate Word width:

8. 2004 MAPLD, Paper 190 JJ Wang 8 ACTgen Creates EDAC-RAM

9. 2004 MAPLD, Paper 190 JJ Wang 9 EDAC-RAM Implementation

10. 2004 MAPLD, Paper 190 JJ Wang 10 EDAC-RAM Heavy Ion Beam Test Test logic designed by ACTgen macro Beam test uses very high fluxes (1x10 4 -1x10 5 Ions/cm 2 /sec) Have to turn on scrubbing during irradiation Test ports not used ECC and scrubbing are tested simultaneously because scrubbing alone cannot reduce SEU

11. 2004 MAPLD, Paper 190 JJ Wang 11 EDAC-RAM BNL Test Data

12. 2004 MAPLD, Paper 190 JJ Wang 12 EDAC-RAM SEU Cross-Section per 8-bit Word Weibull Fit

13. 2004 MAPLD, Paper 190 JJ Wang 13 RAM SEU Cross-Section per Single Bit

14. 2004 MAPLD, Paper 190 JJ Wang 14 EDAC-RAM SEU Rate Prediction Use Space Radiation 4.5 simulator: Weibull parameters: LET 0 =30MeVcm 2 /mg, width=10MeVcm 2 /mg, shape=1.5, saturation cross-section=3.91x10 -9 cm 2 Active volume: depth=0.15µm, funnel depth=0.3µm Environment: GEO solar minimum Shielding: 100mil Aluminum Upsets Rate Boundary: 8-bit word is < 2.55x10 -11 upsets/wordday 16-bit word is < 1.57x10 -10 upsets/wordday 32-bit word is < 4.18x10 -10 upsets/wordday

15. 2004 MAPLD, Paper 190 JJ Wang 15 EDAC-RAM TAMU Test Data

16. 2004 MAPLD, Paper 190 JJ Wang 16 Scrubbing Rate Dependence Predicted upsets derived from single-bit-upset cross section and probability theory Prediction and Experiment match at high upsets but not at low upsets Low upsets in Experiment may be due to SET and noise Clock FreqRefresh PeriodExper UpsetPredicted Upset 2 MHz512 µs10.00265 100 kHz10 ms20.0529 10 kHz0.1 s50.529 1 kHz1 s85.29 100 Hz10 s5452.9 No Scrubbing100 s150166

17. 2004 MAPLD, Paper 190 JJ Wang 17 Conclusions Hard-wired TMR flip-flop is radiation hard. The measured upset errors in hardened flip-flops are probably due to SET and noise. EDAC-RAM is radiation hard, which means the ECC scheme and scrubbing are performing as expected. Low level upsets measured in EDAC-RAM are probably due to SET and noise.