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Crossing-Free Boundary Labeling Using Hyperleaders Chun-Cheng Lin Taipei Municipal University of Education.

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Presentation on theme: "Crossing-Free Boundary Labeling Using Hyperleaders Chun-Cheng Lin Taipei Municipal University of Education."— Presentation transcript:

1 Crossing-Free Boundary Labeling Using Hyperleaders Chun-Cheng Lin Taipei Municipal University of Education

2 2 Outline Introduction Motivations Our results One-side case  O(n log n) time solvable Two-side case  O(n 2 ) time solvable Four-side case  simulated annealing Conclusion & Future work

3 3 Map Labeling Point features e.g., city Line features e.g., river Area features e.g., mountain

4 4 Boundary Labeling [Bekos et al., GD 2004] (Bekos & Symvonis, GD 2005) Type-opo leadersType-po ledersType-s leaders Min (total leader length) s.t. #(leader crossing) = 0 1-side, 2-side, 4-side site label leader

5 5 Variants Polygons labelingMulti-stack boundary labeling Type-od leaderType-pd leaderType-do leader 5

6 6 Brown booby Taiwan hill partridge Masked palm civet Hawk Melogale moschata Bamboo partridge Chinese pangolin Mallard Distribution of some animals in Taiwan: Many-Site-to-One-Label Boundary Labeling (a.k.a., Many-to-One Boundary Labeling) (Lin, Kao Yen, 2008) Legend: Brown booby Taiwan hill partridge Masked palm civet Hawk Melogale moschata Bamboo partridge Chinese pangolin Mallard

7 7 Brown booby Masked palm civet Hawk Chinese pangolin Taiwan hill partridge Melogale moschata Bamboo partridge Mallard Two-Side Many-to-One Boundary Labeling

8 8 One More Example – Server Motherboard – 8 DIMMs ATX Power Supply 2 LAN Ports Battery BIOS 2 Chipsets 6 SATA ConnectorsIDE Slot PS2 Port USB Port COM Port VGA Port 4 CPUs 6 Expansion Slots

9 9 Many-to-One Boundary Labeling Using Hyperleaders & Dummy Labels Type-opo hyperleaders & dummy labels Main features No confusion and crossings between leaders Suitable for labeling the sites with clusters One-side and two-side cases are suitable for the maps with vertical-strip shapes R Track Routing Area l1’l1’ l1l1 l2l2 No leader crossings adding dummy labels R l1l1 Track Routing Area l2l2 hyper-leader dummy label

10 10 Our Concerned Problem Minimizing the number of dummy labels s.t. there are no leader crossings. Furthermore, after determining # & pos of dummy labels, the number of bends is minimized; the total leader length is minimized. R

11 11 Our Theoretical Results for Many-to-One Boundary Labeling objective# of sides leader type complexitysolution Min #(crossing) 1-sideopoNP-complete3-approx. 2-sideopoNP-complete 3(1+.301/c)- approx. 1-sidepoNP-completeheuristic 2-sidepoNP-completeheuristic Min Total leader length any polynomial time Min #(dummy labels) 1-sideopoO(n log n) 2-sideopoO(n2)O(n2) Note that c is a number depending on the sum of edge weights.

12 12 RRR g1g1 g2g2 g3g3 g4g4 g5g5 g6g6 g7g7 g8g8 R g1g1 g2g2 g3g3 g4g4 g5g5 g6g6 g7g7 g8g8 l1l2l3l4l5l6l7l8l1l2l3l4l5l6l7l8 One-Side Case InputStep 1.Step 2. Observation. Only the order of y-coordinates of sites matters. Step 3.

13 13 How to Route Hyperleaders?  R gigi l i-1 lili R gigi lili yp(li)yp(li) R gigi lili l i+1 yp(li)yp(li) R gigi lili R gigi lili  yp(li)yp(li) Push i to stack S. (the routing of g i is determined after the routing of g i+1 is determined) R gigi lili l i+1 yp(li)yp(li) R  gigi lili l i+1  R gigi l i-1 lili R gigi lili yp(li)yp(li)  R gigi lili l i+1 

14 L Two-Side Case Step 1.Step 2. R Scan from the top to the bottom. Each label is placed on the right or the left line. If moving labels in L to R does not result in any dummy label, the concerned label is placed on the same line as its guy; o.w.... its recently shown guy. the concerned label R g1g1 g2g2 g3g3 g4g4 g5g5 g6g6 g7g7 g8g8 14

15 15 An Example R Move to the same side of its recently shown guy, if no crossing. Make the numbers of components on both sides as equal as possible

16 16 An Example (cont.) R

17 17 Many-to-One Boundary Labeling The original New 8 DIMMs ATX Power Supply 2 LAN Ports Battery BIOS 2 Chipsets 6 SATAIDE Slot PS2 Port USB Port COM Port VGA Port 4 CPUs 6 Expansion 6 SATA 2 CPUs 2 DIMMs ATX Power Supply Battery BIOS 2 Chipsets 6 DIMMs IDE Slot PS2 Port 6 DIMMs COM Port VGA Port 2 LAN Ports 6 Expansion 2 CPUs

18 18 Our Results objective# of sides leader type Complexity * Minimize #(dummy nodes) 1-sideopoO(n log n) 2-sideopoO(n2)O(n2) * Note that n is the number of sites.

19 19 Four-side case [Bekos et al., 2007] Determining which sites are connected to one of the four sides so that the objective is achieved leads to the NP-hard Partition problem Use the simulated annealing (SA) to solve the four-side case

20 20 Simulated Annealing for 4-side case Configuration Corresponded to a site p Site p divides the map into four regions A 1 -A 4 Initial configuration A configuration where the sites in each region are as equal as possible Neighbor Randomly select a corner c of the map Rotate the line connected to c around c in counterclockwise direction The configuration corresponding to the first scanned site is selected as the neighbor Energy cost function = The cooling schedule is based on the previous work p A1A1 A2A2 A3A3 A4A4 p  (normalized # of dummy labels) + (1- )(normalized total leader length) c

21 21 Statistics

22 Experimental Results (I) 22

23 Experimental Results (II) 23

24 24 A Practical Example

25 25 Conclusion Crossing-free many-to-one boundary labeling using hyperleaders (and dummy labels) 1-side case  O(n log n) time for dummy label min. problem 2-side case  O(n 2 ) time for dummy label min. problem 4-side case  simulated annealing 6 SATA 2 CPUs 2 DIMMs ATX Power Supply Battery BIOS 2 Chipsets 6 DIMMs IDE Slot PS2 Port 6 DIMMs COM Port VGA Port 2 LAN Ports 6 Expansion 2 CPUs

26 26 Future work Considering other kinds of leaders R l1l1 l2l2 l3l3 l4l4 l5l5 R l1l1 l2l2 l3l3 l4l4 l5l5 R l1l1 l2l2 l3l3 l4l4 l5l5 MST Steiner Tree Steiner points

27 Thank you for your attention!


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