1. Encryption for Mobile Computing By Erik Olson Woojin Yu

2. Encryption Algorithms DES and 3DES RC5 RC6 – AES Finalist Twofish- AES Finalist

3. DES and 3DES DES - International Standard, 1970’s 3DES – repeated encryption with DES Extensive usage of permutation, table look-ups, and rotational shifts 56 bit key – weak encryption

4. RC5 Fast block cipher By Ron Rivest at RSA in 1994 Based on integer addition, data dependent rotational shifts and XOR’s Very simple, but powerful Patented

5. RC6 Based on RC5 algorithm One finalist for AES 128 bit blocks for AES Flexible

6. Twofish AES finalist XOR’s, 32 bit and 4 bit rotational shifts, table lookups, and matrix operations Scalable and parameterizable Some operations can be done in parallel

7. Processor in Our Survey Motorola DragonBall EZ - 68K core - Primarily used in Palm Pilots - 16.58 Mhz - 2.7 MIPS rating

8. Setup and Makekey Shifts and Rotational Shifts –A=A>>8 –ROTL(x,n)= (x > 0x20-(n&0x1f)) Word Swapping –A->B, B->A Extensive usage of loops Array operations –S[I]=S[I-1]+4

9. 3DES Setup

10. RC5 Setup

11. RC6 Setup

12. Twofish Setup

13. Core Operations Rotational Shifts –ROTL(x,n)= (x > 0x20-(n&0x1f)) –ROTR(x,n)= (x>>(n & 0x1f))|(x << 0x20-(n&0x1f)) XOR –A=A^B

14. Core Op Cont’d Integer Operations –A=A+S[0] Bit Permutation –A=01001110 SP={5,7,1,3,2,8,4,6} A=11001001 after permutation Using Constants –P=0xb7e15163, –A=A^P

15. 3DES Core

16. RC5 Core

17. RC6 Core

18. Twofish Core

19. Analysis & Improvement Using Rotational Shift instruction Implementing special shifting unit LSR and LSL dominate the clock cycles Minimize Move Instruction/Penalty

20. Analysis Cont’d Improvement using ROT instruction –1.5 times speed up in encryption core Improvement using fast rotation HW –2 times speed up in encryption core

21. Analysis Cont’d 3DES Core –6.1 Kbps RC5 Core –121 Kbps –Improved version : 272 Kbps RC6 Core –87 Kbps –Improved version : 187 Kbps Twofish –12.8 Kbps

22. Conclusion Dominance of shifts and rotational shifts in all encryption algorithms Limited improvement provided by the specialized hardware Importance of algorithm choice for optimal usage

23. Future Recommendations Analysis on Windows CE processors – Hitachi SH3 and StrongArm Analysis involving more instruction parallelism Analysis on configurable processors - Tensilica