1. The Layered Protocol Wrappers 1 Florian Braun, Henry Fu The Layered Protocol Wrappers: A Solution to Streamline Networking Functions to Process ATM Cells, AAL5 Frames, IP Packets, and UDP Datagrams Florian Braun, Henry Fu Washington University Applied Research Lab Supported by: NSF ANI-0096052 and Xilinx Corp. http://www.arl.wustl.edu/arl/projects/fpx/wrappers/ florian@arl.wustl.edu, hwf1@arl.wustl.edu

2. The Layered Protocol Wrappers 2 Florian Braun, Henry Fu The Layered Protocol Wrappers The Layered Protocol Wrappers Library –A circuit that streamline the networking functions to process ATM cells, AAL5 frames, IP packets, and UDP datagrams –A layered design that consists different processing circuit in each layer –Allows application to be implemented at a level where important details are exposed and irrelevant details are hidden

3. The Layered Protocol Wrappers 3 Florian Braun, Henry Fu Basic Concept of the Protocol Wrappers Application Wrapper

4. The Layered Protocol Wrappers 4 Florian Braun, Henry Fu Overview of the Protocol Wrappers The Protocol Wrappers is composed of four circuits: –Cell Processor processes raw ATM cells between network interfaces –Frame Processor processes variable length AAL5 frames –IP Processor processes IP packets –UDP Processor sends and receives UDP datagrams

5. The Layered Protocol Wrappers 5 Florian Braun, Henry Fu Overview of the Layered Protocol Wrappers UDP Processor IP Processor Cell Processor Frame Processor Data Output Data Input Application-level Hardware Module Interfaces to Off-Chip Memories

6. The Layered Protocol Wrappers 6 Florian Braun, Henry Fu The Cell Processor The Cell Processor handles ATM Cells, and provides valid ATM Cells control signals to the cell level application or the Frame Processor Checks the HEC and drops erroneous cells Dispatch cells to application or bypass Handles control cells Recomputes HEC for outgoing cells

7. The Layered Protocol Wrappers 7 Florian Braun, Henry Fu The Cell Processor (More) Data Flow inside the Cell Processor Cells Control Dispatch Check HEC Set App or Frame Processor

8. The Layered Protocol Wrappers 8 Florian Braun, Henry Fu The Frame Processor The Frame Processor handles AAL5 frames and provides valid AAL5 frame control signals to the application or the IP Processor – Detects AAL5 frame boundaries – Handles CRC – Segments data into cells

9. The Layered Protocol Wrappers 9 Florian Braun, Henry Fu The Frame Processor (More) Data Flow inside the Frame Processor Frame Detection Cell AAL5CRC ation Segment App or IP Processor

10. The Layered Protocol Wrappers 10 Florian Braun, Henry Fu The IP Processor The IP Processor handles IP packets and provides valid IP packet control signals to the application or the UDP Processor Verify IP version Check Header Checksum for application Drop packet if the Header Checksum fails Decrease TTL field (ev. ICMP msg) Signal start of payload (SOP) Recompute Header Checksum

11. The Layered Protocol Wrappers 11 Florian Braun, Henry Fu The IP Processor (More) Data Flow inside the IP Processor IP Detect TTLDec Checksum + Checksum App or UDP Processor

12. The Layered Protocol Wrappers 12 Florian Braun, Henry Fu The IP Processor (More) The IP Packet is encapsulated by a ATM Cell TTL ATM Header IP Header VerHLToS Proto Packet Length Fragment Checksum IPID Source IP address Destination IP address Payload

13. The Layered Protocol Wrappers 13 Florian Braun, Henry Fu The UDP Processor The UDP Processor handles UDP datagrams and provide valid UDP datagram signal to the application Check for protocol ID (17) Signal start of datagram (SOD) Handle UDP checksum

14. The Layered Protocol Wrappers 14 Florian Braun, Henry Fu The UDP Processor (More) Data Flow inside the UDP Processor UDP Detect Checksum Set App or UDP Processor

15. The Layered Protocol Wrappers 15 Florian Braun, Henry Fu The UDP Processor (More) The UDP Datagram is encapsulated by a IP Packet inside an ATM Cell UDP Header IP Header Src PortDest Port LengthChecksum Payload ATM Header VerHL Proto ToS TTLChecksum Fragment Packet Len IPID Source IP address Destination IP address

16. The Layered Protocol Wrappers 16 Florian Braun, Henry Fu Synthesis Results Required Space and Speed of the Layereed Protocol Wrappers 114550UDP Processor 1091009IP Processor 1161251Frame Processor 125781Cell Processor Speed/MHzSpace/LUTs

17. The Layered Protocol Wrappers 17 Florian Braun, Henry Fu Performance Results InputOutputInput 202274439 UDP Processor 197243936 IP Processor 31102221 Frame Processor 6464 Cell Processor Delay for long packagesDelay for short packages Output

18. The Layered Protocol Wrappers 18 Florian Braun, Henry Fu The Layered Protocol Wrappers Package The Protocol Wrappers Package –Detailed Information http://www.arl.wustl.edu/arl/projects/fpx/wrappers –Downloadable TAR File http://www.arl.wustl.edu/arl/projects/fpx/wrappers/- wrappers.tar –Technical Report http://www.arl.wustl.edu/arl/projects/fpx/wrappers/- wucs-01-10.pdf

19. The Layered Protocol Wrappers 19 Florian Braun, Henry Fu Contents of the Layered Protocol Wrappers Access the Protocol Wrappers Package –Cell Processor cellwrapper.vhdl, the VHDL instantiation file cellproc_sim.vhd, the VHDL simulation file cellproc.edn, the EDIF Macro synthesis file –Frame Processor framewrapper.vhdl, the VHDL instantiation file frameproc_sim.vhd, the VHDL simulation file frameproc.edn, the EDIF Macro synthesis file

20. The Layered Protocol Wrappers 20 Florian Braun, Henry Fu Contents of the Protocol Wrappers Package –IP Processor ipwrapper.vhdl, the VHDL instantiation file ipproc_sim.vhd, the VHDL simulation file ipproc.edn, the EDIF Macro synthesis file –UDP Processor udpwrapper.vhdl, the VHDL instantiation file udpproc_sim.vhd, the VHDL simulation file udpproc.edn, the EDIF Macro synthesis file –COREGEN Components

21. The Layered Protocol Wrappers 21 Florian Braun, Henry Fu Combining Multiple Processors Cell Processor only  Cell Processor Cell + Frame Processors  Frame Wrapper Cell + Frame + IP Processors  IP Wrapper Cell + Frame + IP + UDP Processors  UDP Wrapper

22. The Layered Protocol Wrappers 22 Florian Braun, Henry Fu Wrappers Example: An UDP Application UDP Processor UDP Application IP Processor Cell Processor Frame Processor Output Input UDP Wrapper

23. The Layered Protocol Wrappers 23 Florian Braun, Henry Fu Building an UDP Application The user only needs to handle input signals from the UDP Wrapper –Input Signals: D_MOD_IN (data input) DataEn_MOD_IN (data enable) SOF_MOD_IN (start of frame) SOD_MOD_IN (start of datagram) EOF_MOD_IN (end of frame) TCA_MOD_IN (congestion control)

24. The Layered Protocol Wrappers 24 Florian Braun, Henry Fu Building an UDP Application (More) Similarly, the user only needs to handle output signals to the UDP Wrapper –Output Signals: D_OUT_MOD (data output) DataEn_OUT_MOD (data enable) SOF_OUT_MOD (start of frame) SOD_OUT_MOD (start of datagram) EOF_OUT_MOD (end of frame) TCA_OUT_MOD (congestion control)

25. The Layered Protocol Wrappers 25 Florian Braun, Henry Fu Building an UDP Application (More) Other important input signals –CLK Clock signal for module 100 MHz –Reset_l Synchronous reset Low for 1 clock cycle to reset state machines Set by reconfiguration logic

26. The Layered Protocol Wrappers 26 Florian Braun, Henry Fu Explanation of Control Signals SOF_MOD_IN + SOF_OUT_MOD –High for 1 clock cycle during first ATM header word –Signals start of a new AAL5 frame –Note: HEC is not sent after this signal EOF_MOD_IN + EOF_OUT_MOD –High during 1 clock cycle of last payload word of datagram –Followed by the two trailer words of the AAL5 frame

27. The Layered Protocol Wrappers 27 Florian Braun, Henry Fu Explanation of Control Signals (More) DataEn_MOD_IN + DataEn_OUT_MOD –High during valid payload data –High during trailer words (after EOF) SOD_MOD_IN + SOD_OUT_MOD –High for 1 clock cycle during first word of UDP header –UDP payload starts after two valid payload words (check Data Enable) –Not enabled if not a UDP packet

28. The Layered Protocol Wrappers 28 Florian Braun, Henry Fu Explanation of Control Signals (More) D_MOD_IN + D_OUT_MOD –32 bit wide data bus TCA_MOD_IN + TCA_OUT_MOD –TCA signal is high when data can be accepted, low if no data should be sent –Wrappers back-propagate TCA to the NID –Data in pipeline will still be forwarded (~cell time) –IP wrapper has big packet buffer for outgoing data

29. The Layered Protocol Wrappers 29 Florian Braun, Henry Fu Diagram of Input Signals

30. The Layered Protocol Wrappers 30 Florian Braun, Henry Fu Wrapper Example: A Pass-through Circuit The Protocol Wrappers Example Package –Visit http://www.arl.wustl.edu/arl/projects/fpx/fpx_kcpsm/ –Download the package Right click on WrapperExample.tar.gz Save it to h:\ –Start Cygwin Bash Shell Engineering > FPGA Tools > Cygwin Bash Shell

31. The Layered Protocol Wrappers 31 Florian Braun, Henry Fu Wrappers Example: A Pass-through Circuit –Extract the tar file cd /cygdrive/h/ gunzip WrapperExample.tar.gz tar xvf WrapperExample.tar cd WrapperExample –Examine the content of the package WrapperExample/sim/, simulation directory WrapperExample/syn/, synthesis directory WrapperExample/vhdl/, vhdl source directory WRapperExample/wrappers/, Wrappers directory

32. The Layered Protocol Wrappers 32 Florian Braun, Henry Fu Input / Output Signals of the Module ENTITY ExampleModule IS PORT ( -- Clock & Reset clk : in STD_LOGIC; -- 100MHz global clock reset_l : in STD_LOGIC; -- Synchronous reset, asserted-low -- Enable & Ready -- Handshake for module reconfiguration. enable_l : in STD_LOGIC; -- Asserted low ready_l : out STD_LOGIC; -- Asserted low -- Cell Input Interface soc_mod_in : in STD_LOGIC; -- Start of cell d_mod_in : in STD_LOGIC_VECTOR(31 downto 0); -- 32-bit data tca_mod_in : out STD_LOGIC; -- Transmit cell available -- Cell Output Interface soc_out_mod : out STD_LOGIC; -- Start of cell d_out_mod : out STD_LOGIC_VECTOR(31 downto 0); -- 32-bit data tca_out_mod : in STD_LOGIC; -- Test Data Output test_data : out STD_LOGIC_VECTOR(31 downto 0)); end ExampleModule; Clock & Reset Enable & Ready Cell Input Interface Cell Output Interface

33. The Layered Protocol Wrappers 33 Florian Braun, Henry Fu Input / Output Signals of the UDP Wrapper component udpwrapper port ( CLK : in std_logic; -- clock Reset_l : in std_logic; -- reset Enable_l : in std_logic; -- enable Ready_l : out std_logic; -- ready SOC_MOD_IN : in std_logic; -- start of cell D_MOD_IN : in std_logic_vector (31 downto 0); -- data TCA_MOD_IN : out std_logic; -- transmit cell available D_OUT_APPL : out std_logic_vector (31 downto 0); -- data to appl DataEn_OUT_APPL : out std_logic; -- data enable SOF_OUT_APPL : out std_logic; -- start of frame EOF_OUT_APPL : out std_logic; -- end of frame SOD_OUT_APPL : out std_logic; -- start of datagram TCA_OUT_APPL : in std_logic; -- congestion control D_APPL_IN : in std_logic_vector (31 downto 0); -- data from appl DataEn_APPL_IN : in std_logic; -- data enable SOF_APPL_IN : in std_logic; -- start of frame EOF_APPL_IN : in std_logic; -- end of frame SOD_APPL_IN : in std_logic; -- start of datagram TCA_APPL_IN : out std_logic; -- congestion control SOC_OUT_MOD : out std_logic; -- start of cell D_OUT_MOD : out std_logic_vector (31 downto 0); -- data TCA_OUT_MOD : in std_logic); -- transmit cell available end component; Coming From Cell Interface Going To Application Interface Coming from Application Input Interface Going to Cell Interface

34. The Layered Protocol Wrappers 34 Florian Braun, Henry Fu Input / Output Signals of the ExampleApp component ExampleApp port ( CLK : in std_logic; -- clock Reset_l : in std_logic; -- reset D_MOD_IN : in std_logic_vector (31 downto 0); -- data DataEn_MOD_IN : in std_logic; -- data enable SOF_MOD_IN : in std_logic; -- start of frame EOF_MOD_IN : in std_logic; -- end of frame SOD_MOD_IN : in std_logic; -- start of datagram TCA_MOD_IN : out std_logic; -- congestion control D_OUT_MOD : out std_logic_vector (31 downto 0); -- data DataEn_OUT_MOD : out std_logic; -- data enable SOF_OUT_MOD : out std_logic; -- start of frame EOF_OUT_MOD : out std_logic; -- end of frame SOD_OUT_MOD : out std_logic; -- start of datagram TCA_OUT_MOD : in std_logic); -- congestion control end component; Application only needs to handle UDP signals

35. The Layered Protocol Wrappers 35 Florian Braun, Henry Fu Implementation of the ExampleApp Examine the “exampleapp.vhd” –A flip-flop that passes data and control signals through –Can be extended to implement other more complex network control functions –Will be used as the framework for the coming ROT13 exercise

36. The Layered Protocol Wrappers 36 Florian Braun, Henry Fu Simulating the ExampleApp Modelsim is used to simulate the ExampleApp –Go to the simulation directory cd WrapperExample/sim/ –Compile the module and start Modelsim Make compile Make sim –In Modelsim main window, type: do testbench.do run 3000

37. The Layered Protocol Wrappers 37 Florian Braun, Henry Fu Simulating the ExampleApp (More) The input data at the line card level

38. The Layered Protocol Wrappers 38 Florian Braun, Henry Fu Simulating the ExampleApp (More) The input data at the UDP Wrapper level

39. The Layered Protocol Wrappers 39 Florian Braun, Henry Fu Simulating the ExampleApp (More) The input data at the application level

40. The Layered Protocol Wrappers 40 Florian Braun, Henry Fu Simulating the ExampleApp (More) The output data at the application level

41. The Layered Protocol Wrappers 41 Florian Braun, Henry Fu Simulating the ExampleApp (More) The output data at the UDP Wrapper level

42. The Layered Protocol Wrappers 42 Florian Braun, Henry Fu Simulating the ExampleApp (More) The output data at the line card level

43. The Layered Protocol Wrappers 43 Florian Braun, Henry Fu Conclusion In this Layered Protocol Wrappers Example –Shows the components of the UDP Wrapper –Shows the function of the UDP Wrapper –Shows how to instantiate and use the UDP Wrapper –Examines the control signals at various levels of data processing –Sets up the framework for ROT13 exercise