1. 1 Copyright © Monash University ATM Switch Design Philip Branch Centre for Telecommunications and Information Engineering (CTIE) Monash University http://www.anspag.monash.edu.au/~pbranch/masters.ppt

2. 2 Copyright © Monash University ATM Switching Outline Switching terms and requirements Switch Architectures –cross bar, multiple bus, multistage –routing in multistage switches Buffering schemes in switches Buffer management Performance Measures

3. 3 Copyright © Monash University ATM Switching Terms Switching Switching Element Switching Fabric Switching System

4. 4 Copyright © Monash University ATM Switch Requirements Flexible switching rates Broadcast and Multicast Low cell loss probability Cell Sequence integrity. High speed switching. Cell header processing. –VPI/VCI translation

5. 5 Copyright © Monash University Switch types Workgroup switches Campus switches Core switches

6. 6 Copyright © Monash University Types of Switching Backplane Blocking –Routing Conflicts –Cells are lost if no internal buffers. –Cells are stored in a queue if there are internal buffers. Non-blocking –No internal blocking. –Buffers at the inputs and/or outputs.

7. 7 Copyright © Monash University ATM Switch Architectures Crossbar –Most campus switches Multiple Bus –Most workgroup switches Multistage –Most core switches

8. 8 Copyright © Monash University Best performance Very expensive for large switches Cost increases as where NXN is the switch size. Crossbar

9. 9 Copyright © Monash University Multiple Bus Lowest cost Poor scalability Poor performance due to bus contention Inputs Outputs Busses

10. 10 Copyright © Monash University Multistage Switches Interconnection of a number of crossbar switching elements. Single path or multiple path. Buffers required to store packets. Very cost effective. Highly scalable.

11. 11 Copyright © Monash University Multistage Switching Fabric

12. 12 Copyright © Monash University Routing in Multistage Switches Self routing using destination tags Internal routing conflicts may –reduce the throughput, –increase the delay and –increase the cell loss in a switch.

13. 13 Copyright © Monash University Self-Routing Principle VPI/VCI translation only at the input of the switching network Cell extended by a switching network internal header Cell header extension requires increased internal speed. Suitable for large multistage networks

14. 14 Copyright © Monash University Self-routing (contd.)

15. 15 Copyright © Monash University Self Routing: Example

16. 16 Copyright © Monash University Multicast with Self-Routing

17. 17 Copyright © Monash University Tree Saturation Hot spot traffic – A lot of traffic may be directed to a particular output. Tree saturation reduces the performance of the switch Saturated tree blocks traffic to other (non hot) outputs as well.

18. 18 Copyright © Monash University Contention in a Multi-stage Switch

19. 19 Copyright © Monash University Batcher-Banyan Switch A Banyan network has no internal conflict if cells are arranged in ascending or descending order of output destination. A Batcher network is used to sort cells in ascending order.

20. 20 Copyright © Monash University Batcher-Banyan (contd.)

21. 21 Copyright © Monash University Table-controlled VPI/VCI translation VPI/VCI translation at each switching element. Cell length need not be altered. Table contents are updated during connection set-up.

22. 22 Copyright © Monash University Table-controlled (contd.)

23. 23 Copyright © Monash University Buffering in Switches Buffers store the cells that lose routing conflicts. Location of buffers: –Internally, Externally –Input, Output, Shared, Crosspoint

24. 24 Copyright © Monash University Input Buffered Switch

25. 25 Copyright © Monash University Input Buffers Head of line blocking reduces throughput Inefficient utilisation of buffer space Simple buffer management

26. 26 Copyright © Monash University Head-of-Line Blocking

27. 27 Copyright © Monash University Output Buffered Switch

28. 28 Copyright © Monash University Output Buffers No head of line blocking Inefficient utilisation of buffer space Requires expensive high speed buffers

29. 29 Copyright © Monash University Shared Buffer

30. 30 Copyright © Monash University Shared Buffer High buffer utilisation. Needs least amount of buffer space. Buffer hogging with non uniform traffic. Complex buffer management strategy. Needs expensive high speed buffers.

31. 31 Copyright © Monash University Crosspoint Buffer

32. 32 Copyright © Monash University Crosspoint Buffer Combines the advantages of input and output buffers Inefficient utilisation of buffer space Simple buffer management

33. 33 Copyright © Monash University Buffer Size Requirements Buffer sizes for average load of 85% at each input and a permissible cell loss probability of 10 -9

34. 34 Copyright © Monash University Buffer Management Queuing –How to organise buffered cells Scheduling –When and in what order to service queues

35. 35 Copyright © Monash University Buffer Management Which cell to transmit next? Arbitration strategies based on –Random –fairness –minimise cell loss –minimise cell delay variation

36. 36 Copyright © Monash University Arbitration Strategies State dependent: –Longest queue served first –Lengths of buffers have to be compared Delay dependent: –Queue having the maximum delay served first –Overhead in storing order of arrival information

37. 37 Copyright © Monash University Buffer Queuing Policies First in - First out (FIFO) Strict Priority Fair Queueing (Per VC queueing) Weighted Round Robin Weighted Fair Queuing

38. 38 Copyright © Monash University Performance Measures Throughput: Number of cells switched per unit time. Cell loss probability: Loss from routing conflicts or insufficient capacity Cell delay: Delay inside switch. –Switching delay: fixed –Queueing delay: variable –jitter: Cell delay variation.

39. 39 Copyright © Monash University Conclusion –Switching terms and requirements –Switch architectures –Multistage switches self routing Batcher-Banyan switch –Buffering schemes Input, output, shared, crosspoint –Output buffer management –Performance measures

40. 40 Copyright © Monash University Questions An ATM switch is functioning normally, until a video server and video client are connected to it. When the video is played back from the server through the switch, other (low bandwidth) applications using the switch fail. The video delivered is jerky. What are some possible explanations for this?