1. Logic Synthesis For Low Power CMOS Digital Design

2. Outlines Power consumption model Dynamic power minimization –Reduction of output gate transitions i. Logic synthesis for low power ii. State assignment for low power –Turning-off portions of a circuit Leakage power minimization

4. Power Dissipation Static dissipation due to leakage circuit Short-circuit dissipation Charge and discharge of a load capacitor V in V out V DD GND o

5. Power Dissipation Model P: the power dissipation for a gate, C: the load capacitance, V dd : the supply voltage, T cyc : the clock period, E: the transition count of the gate per clock cycle.

6. How to Compute Transition Density? signal probability P 1 (g): the probability of a logic 1 at the output of gate g signal probability P 0 (g): the probability of a logic 0 at the output of gate g, 1-P 1 (g) signal transition probability(density) P t 0 1 or 1 0 1 2 3 4 5 i1 i2 i3 i4

7. Simulation-based Computation Logic Simulator Logic waveform of each node Input-pattern dependent Two many input patterns

8. Probability-based Computation A simple method : g i1 P 0 (g) = P 1 (g) = P 1 (i1) P 0 (i1) P 1 (g) = P 1 (i1) *P 1 (i2) P 0 (g) = 1-P 1 (g) P 0 (g) = P 0 (i1) *P 0 (i2) P 1 (g) = 1-P 0 (g) g g i1 i2 i1 i2

9. Probability-based Computation A simple method : 1 2 3 4 5 i1 i2 i3 i4 Time titi t i+1 P 0 (e) P 1 (e) P 0 (e)..... (1-P 1 (g))*P 1 (g) P 1 (g)*(1-P 1 (g)) => 2*P 1 (g)*(1-P 1 (g)) Inaccuracy of the simple model – Temporal relations – Spatial relations

10. Technology Mapping For Low Power (a) Circuit to be mapped Gate Type Area Intrinsic Input Load Cap. Cap. INV 928 0.1029 0.0514 NAND2 1392 0.1421 0.0747 NAND3 1856 0.1768 0.0868 AOI33 3248 0.3526 0.1063 (b) Characteristics of the Library Pt=0.179 G1 G2 G3 a b c d e f Pt=0.109 out

11. Technology Mapping For Low Power G1 G2 G3 a b c d e f out AOI33 INV Area Cost: 4176 Power Cost: 0.0907 (c) Minimum-Area Mapping out G1 G2 G3 a b c d e f NAND3 NAND2 WIRE NAND3 Area Cost: 5104 Power Cost: 0.0803 (d) Minimum-Power Mapping

12. State Assignment S2S2 S1S1 S3S3 01 -0 00 10 0- 1- 01 -0 11 Combinational Logic PIPO PS NS u1u1 u2u2 v1v1 v2v2 S4S4

13. State Assignment for Low Power Design Uneven distribution of state transitions in Finite State Machine State assignment such that states with high transitions are given state codes of short distance Minimize –w(s,t): transition between s and t (power cost)

14. State Probability Model SkSk SiSi I k,i Prob(S i ) = where PS(S i ) : the set of immediately previous states of S i, Prob(I k,i ): the probability of input pattern I k,i

15. State Probability Model (cont.) The summation of all states probability is equal to 1, therefore The state probabilities of S i ’s can be obtained by solving the linear system using the Cholesky Decomposition method.

16. Partitioning of a Controller START s4 s6 s5 s2 s7 s3 M1 M2 1/00 0/00 0/01 0/00 1/10 0/10 1/10 1/01 0/00 1/10 0/00 00/0 1/00 Turning Off Portions of a Circuit

17. Four Questions: 1. How do we determine the submachine to be turned on in each clock cycle? 2. When an inactive submachine becomes active, how do we set it to the correct state for the next clock cycle? 3. How does an active submachine relinquish control and pass it to the submachine which will become active in the next clock cycle? 4. Physically, how do we turn off a piece of combinational logic?

18. Question 1 How do we determine which submachine to be turned on? current state + input next state the submachine to be turned on To simplify the control logic: state code: –States in the same submachine will have the same control bits. –The remaining bits will be used to distinguish among states in the same submachine. need control logic to make this decision control bits

19. State Code of the Sub-machines START S4 s6 s5 s2 s7 s3 M1 M2 1/00 0/00 0/01 0/00 1/10 0/10 1/10 1/01 0/00 1/10 0/00 00/0 1/00

20. Question 2 When an inactive submachine becomes active, how do we set it to the correct state?  Include the crossing transition in the state transition table of the submachine

21. An Example s0 s1 s2 s3 s4 s5 1 1 0 1 1 0 M1M2 input present state next state output M1 0 1 0 1 0 1 s0 s1 s2 s1 s3 s2 s3 s1 s5 101011101011 input present state next state output M2 0 1 0 1 0 1 s3 s4 s5 s0 s1 s5 s4 s3 101000101000

22. Question 3 How does an active submachine relinquish control to allow another submachine to become active?  The above state assignment will allow control to be transferred from one machine to another with no additional circuitry

23. Question 4 How we actually turn on and off a piece of combinational logic? mux_1 2 1 mux mux_2 2 1 mux mux_3 2 1 mux mux_4 2 1 mux mux_5 2 1 mux O1O2 Com_1(M 1)Com_2(M 2) 1 2 decoder e1 e2 ABCDEFGH X1 control_1 FF 1 FF 2 FF 3

24. Two Subproblems to Solve 1. Partitioning a Finite State Machine into submachines 2. State assignment for submachines

25. Leakage Power Optimization –Gate threshold voltage assignment high threshold voltage: –leakage power↓ –delay↑ low threshold voltage: –leakage power ↑ –delay↓

26. How to Reduce Leakage Power Without Performance Loss 1.use low threshold voltage gates for timing optimization 2.compute the slack time of each node 3.find all non-critical nodes and compute cost for each non-critical node 4find candidate nodes for replacement 5replace candidate nodes by high threshold voltage gates to save leakage power 6re-compute the slack time of each node 7if timing requirement is not violated, go to step 3.

27. An Example to Reduce Leakage Power Without Performance Loss Initial solution are all low threshold voltage gates for timing optimization Critical path = w  u  z  x (x,y, z) means (slack, timing cost, power reduction) x y z u wv a b c d e f y (0, 0.5, 1) (0, 0.2, 0.5) (0.5, 0.25, 0.5) (0, 0.5, 0.25) (0.5, 0.25, 1) (0, 0.5, 0.5) x Low threshold voltage gate x High threshold voltage gate

28. An Example to Reduce Leakage Power Without Performance Loss High threshold gate = {v, y} Low threshold gate = {w, u, z, x} Power reduction = 1.5 No performance degradation x y z u wv a b c d e f y (0, 0.5, 1) (0, 0.2, 0.5) (0.25, 0, 0) (0, 0.5, 0.25) (0.25, 0, 0) (0, 0.5, 0.5) (x,y, z) means (slack, timing cost, power reduction) x Low threshold voltage gate x High threshold voltage gate