2. CEG 360/560; EE 451/651 Digital System Design Dr. Travis Doom, Associate Professor Department of Computer Science and Engineering Wright State University Section III: Complex system design

3. CEG 360/560 - EE 451/651 Section III - 2 Outline l Dealing with Complexity l Data unit (Datapath) design –Registers –RTL language –Datapath Construction l Control unit (Controller) design –ASM Charts l Implementation issues –PLDs –ROM –VLSI Design

4. CEG 360/560 - EE 451/651 Section III - 3 Dealing with Complexity l Practical synchronous sequential circuits are too complex to design at the flip-flop level. –A simple 8-bit CPU capable of storing only four values (in four GPRs) has at least 4 x 8 = 32 1-bit state devices! –If the CPU had only 8 inputs it would still require a 2 32 by 2 8 truth table to represent the device. Each of these billion or so entries would have to contain a 32-bit next state. Storing 2 40 32-bit entries would require 4 TB! l K (kilo) 2 10 1024 l M (mega) 2 20 1048576 l G (giga)2 30 1.07 x 10 9 l T (tera) 2 40 1.10 x 10 12 –Simplification would require a 40-variable K-map! l How do we manage complex design?

5. CEG 360/560 - EE 451/651 Section III - 4 Complex System Design l Practical sequential designs, like combinational designs, require a hierarchical approach –Use well defined building blocks l Complex blocks made of simpler blocks (hierarchy) l Examples: Registers, counters l Associate a high-level of behavior with those blocks (abstraction) –Design methodologies based on abstractions can more easily encompass complexity –Common function blocks: registers and counters l ORDER a sequence of high-level behaviors that (when executed in the proper order) solves the overall problem –Like computer programming!

6. CEG 360/560 - EE 451/651 Section III - 5 Decomposing a Design: Control and Data l Complex designs are generally broken down into to high-level abstractions. –The datapath is home to one or more datapath components that provide higher-level functionality (viewable at the register transfer level) –The control unit controls the sequence in which the datapath functions are performed in order to perform the system task Control UnitDatapath Control Signals Status Signals Control Outputs Data Inputs Control Inputs Data Outputs

7. CEG 360/560 - EE 451/651 Section III - 6 Outline l Dealing with Complexity l Data unit (Datapath) design –Registers –RTL language –Datapath Construction l Control unit (Controller) design –ASM Charts l Implementation issues –PLDs –ROM –VLSI Design

8. CEG 360/560 - EE 451/651 Section III - 7 Datapath components l Gates and flip-flops are good building blocks for simple designs l We need more sophisticated building blocks for complex systems l Register-transfer level (RTL) components (aka Datapath components) include medium scale devices such as: –Registers –Counters –ALUs –Multiplexers –Comparators –etc

9. CEG 360/560 - EE 451/651 Section III - 8 MSI Quad/Hex Registers CLK CLR 4Q 3Q 2Q 1Q 74LS175 1D 2D 3D 4D CLK CLR 6Q 5Q 4Q 3Q 2Q 1Q 74LS174 1D 2D 3D 4D 5D 6D D 1Q CLR Q Q /1Q 1D D 2Q CLR Q Q /2Q 2D D 3Q CLR Q Q /3Q 3D D 4Q CLR Q Q /4Q 4D CLK /CLR 74LS175 All four flip-flops use the same clock!

10. CEG 360/560 - EE 451/651 Section III - 9 Octal Register with Parallel Load Enable CLK Load 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q D Q 1D /Load CLK 1Q Why don’t we gate the clock? 1b-mux

11. CEG 360/560 - EE 451/651 Section III - 10 Shift Registers RSI 0 1 1 1 Q3 Q2 Q1 Q0 RSI 0 1 1 Q3 Q2 Q1 Q0 0 1 1 1 LSI Q3 Q2 Q1 Q0 1 1 1 LSI Q3 Q2 Q1 Q0 Often used to rearrange bits or Multiply/Divide by 2 l Multi-bit register that moves data “sideways” left/right ( 1 bit/clock ) –Shift Left (or Shift Down) is towards MSB –Shift Right (or Shift Up) is towards LSB

12. CEG 360/560 - EE 451/651 Section III - 11 Bi-directional Universal Shift Registers Quad Bi-directional Universal (4-bit) PIPO CLK CLR S1 S0 LIN D QD C QC B QB A QA RIN 11 1 10 9 7 6 4 5 3 2 12 13 14 15 74x194 Modes: Hold Load Shift Right Shift Left R L Mode Next state Function S1 S0 QA* QB* QC* QD* Hold 0 0 QA QB QC QD Shift right/up 0 1 RIN QA QB QC Shift left/down 1 0 QB QC QD LIN Load 1 1 A B C D SRG n> S1 Q0  Q1 Qn Block symbol D0  D1 Dn S0 RSI LSI (MSB) (LSB) (SI) (SO)

13. CEG 360/560 - EE 451/651 Section III - 12 Universal SR Schematic RIGHT CLK /CLR LIN D (11) (1) (7) (6) D Q CLK CLR 10 00 11 01 (12) QD S1 S0 SL HO LD SR LEFT 74x194 D Q CLK CLR 01 11 00 10 (15) QA S1 S0 A RIN (10) (9) (3) (2)

14. CEG 360/560 - EE 451/651 Section III - 13 Octal Tri-state Register/Latch CLK OE 74LS374 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q C OE 74LS373 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 1Q 2Q 8Q D Q D Q D Q 1D 2D 8D /OE CLK 74LS374

15. CEG 360/560 - EE 451/651 Section III - 14 Shift Register Applications l State Registers –Shift registers are often used as the state register in a sequential device. Usually, the next state is determined by shifting right and inserting a primary input or output into the next position –Very effective for finite memory machines l Serial Interconnection of Systems –keep interconnection cost low with serial interconnect l Bit Serial Operations –Bit serial operations can be performed quickly through device iteration –Iteration (a purely combinational approach) is expensive (in terms of # of transistors, chip area, power, etc). –A sequential approach allows the reuse of combinational functional units throughout the multi-cycle operation

16. CEG 360/560 - EE 451/651 Section III - 15 Shift Register Applications SDATA Parallel- to-serial converter Parallel Data from A-to-D converter Serial-to- parallel converter Parallel Data to D-to-A converter Control Circuits CLOCK /SYNC Transmitter Control Circuits Receiver CLOCK - 1 bit per clock tick = 2.048 MHz /SYNC - synchronization of start of “frame” SDATA - serial data stream DIGITAL TELEPHONY

17. CEG 360/560 - EE 451/651 Section III - 16 Shift Register Applications... 7650 > x7x7 x6x6 x5x5 x0x0 7650 > y7y7 y6y6 y5y5 y0y0 7650 > FA Cout S Cin A B D Q CLK CLR CLK CLEAR_C z7z7 z6z6 z5z5 z0z0... CTL Sequential Implementation of: Z[7..0] = X[7..0] + Y[7..0] V

18. CEG 360/560 - EE 451/651 Section III - 17 Counters l Counters are registers with extra functions l Clocked sequential circuit with single-cycle state diagram –Modulo-m counter = divide-by-m counter l Most Common: n-bit binary counter, where m = 2 n Ù n flip-flops, counts 0 … 2 n -1 S3 S2 S1 Sm 000 001 010 011 100 101 110 111

19. CEG 360/560 - EE 451/651 Section III - 18 Counting l Common output codes for mod-8 and decimal counters StateBinaryBCDGrayExcess-3Ring Twisted-tail 00000000000001100000001 0000 10010001001010000000010 0001 20100010011010100000100 0011 30110011010011000001000 0111 41000100110011100010000 1111 51010101111100000100000 1110 61100110101100101000000 1100 71110111100101010000000 1000 810001011 910011100

20. CEG 360/560 - EE 451/651 Section III - 19 Asynchronous/Ripple Counter Q Q T Q Q T Q Q T Q Q T CLK Q0 Q1 Q2 Q3 1 bit divide-by-2 2 bit divide-by-4 3 bit divide-by-8 4 bit divide-by-16 Uses Minimal Logic! Tpd = n x Tpd,tff Setup = Tsetup,tff

21. CEG 360/560 - EE 451/651 Section III - 20 Synchronous Counters l All clock inputs connected to common CLK signal –So all flip-flop outputs change simultaneously t CQ after CLK l Synchronous Counters are/have –Faster –More Complex Logic (more “expensive”) –Most Frequently Used Type of Counter l Two types of synchronous counters –Serial –Parallel l Easy to combine iteratively to build bigger counters –Combined counters have serial aspects. If the devices are parallel, then the overall device is “mixed mode”.

22. CEG 360/560 - EE 451/651 Section III - 21 Synchronous Serial Counter l Flip-flops enabled when all lower flip- flops = 1. l Enable propagates serially — limits speed Requires (n-1)  t < T CLK l All outputs change simultaneously t CQ after CLK >T Q EN CLK CNTENQ0 Q1 Q2 Q3 Q EN >T Q EN >T Q EN >T Equation? Delay?  t Tpd = Tpd,tff Tsetup = (n-1)  t + Tsetup,tff

23. CEG 360/560 - EE 451/651 Section III - 22 Synchronous Parallel Counter l Single-level enable logic per flip-flop l Fastest and most complex type of counter Requires  t < T CLK l All outputs change simultaneously t CQ after CLK >T Q EN >T Q EN >T Q EN >T Q EN CLK CNTENQ0 Q1 Q2 Q3 Equation? Delay? Tpd = Tpd,tff Tsetup = Tpd,bigestAND + Tsetup,Tff

24. CEG 360/560 - EE 451/651 Section III - 23 74163 4-bit Synchronous Parallel Counter >CLK CLR LD ENP ENT ABCDABCD QA QB QC QD RCO 74X163 LSB MSB RCO = Ripple Carry Out, when Count = 1111 and ENT = 1 (74161 is the same, but with an asynchronous clear) Common Clock Synchronous Clear Synchronous Load Count Enable = ENP  ENT Load Data Inputs

25. CEG 360/560 - EE 451/651 Section III - 24 74163 State Table InputsCurrent State Next State /CLR /LD ENT ENP QD QC QB QA QD* QC* QB* QA* 0 X X X 1 0 X X 1 1 0 X 1 1 1 0 1 1 1 1 X X X X 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 D C B A QD QC QB QA 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 Clear Load Hold Count.

26. CEG 360/560 - EE 451/651 Section III - 25 74169 Up/Down Counter >CLK UP/DN LD ENP ENT ABCDABCD QA QB QC QD RCO 74X169 UP/DN = 1 = up Ù RCO = 15 UP/DN = 0 = down Ù RCO = 0 up down up Ex: 0,1,2, 1,0,15,14, 15,0,1,2 RCO RCO

27. CEG 360/560 - EE 451/651 Section III - 26 Application - Free Running Modulo-16 Counter >CLK CLR LD ENP ENT ABCDABCD QA QB QC QD RCO 74X163 CLOCK +5 V R Q0 Q1 Q2 Q3

28. CEG 360/560 - EE 451/651 Section III - 27 Modulo-11 Counter [5,6, …, 15, 5, 6,...] >CLK CLR LD ENP ENT ABCDABCD QA QB QC QD RCO 74X163 CLOCK +5 V CNT15/CNT15 Q0 Q1 Q2 Q3 When Count=15 Ù Load 5 (0101) Any Modulus 2 Ù 16 possible 10101010 RCO

29. CEG 360/560 - EE 451/651 Section III - 28 Modulo-11 Counter [0,1,2, …, 10, 0, 1,...] >CLK CLR LD ENP ENT ABCDABCD QA QB QC QD RCO 74X163 CLOCK +5 V Q0 Q1 Q2 Q3 When Count=10 Ù Clear Decode Count 1x1x (10…15) ï Q3  Q1 +5 V

30. CEG 360/560 - EE 451/651 Section III - 29 Cascaded 74163s for 8-bit Counter Up to Modulo-256 >CLK CLR LD ENP ENT ABCDABCD QA QB QC QD RCO 74X163 >CLK CLR LD ENP ENT ABCDABCD QA QB QC QD RCO 74X163 CLOCK /RESET /LOAD CNTEN D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 RCO8

31. CEG 360/560 - EE 451/651 Section III - 30 4-bit, 8-state Johnson Counter l Also known as –twisted-ring counter –Moebius counter l 2n states with n flip-flops –NOT self-correcting RIN A B C D LIN S0 S1 CLR CLK +5 V R 74X194 CLOCK QA QB QC QD Wired as a shift-left shift register Q0 Q1 Q2 Q3 /RESET 74X04

32. CEG 360/560 - EE 451/651 Section III - 31 Design Decomposition l A digital system is a sequential circuit with specified behavior. –A microprocessor is a digital system. l Specifying large digital systems with state tables may be exceptionally difficult, due to the number of states involved. –As in computer programming, most digital systems are designed using a modular, hierarchical approach. –The system is partitioned into modular subsystems. l Each subsystem performs a well defined function with specified interface. –Interconnection the various subsystems though data and control signals results in a digital system.

33. CEG 360/560 - EE 451/651 Section III - 32 Design Decomposition l Most digital systems are partitioned into two top-level modules: –Data Unit (or Datapath): performs data-processing operations. –Control Unit: determines the sequence of these operations. l Datapaths are sequential systems. –the system state is defined by the contents of the registers. –the functionality is the set of defined operations that can be performed on the contents of the registers. –Elementary operations are usually, but not always, performed in parallel on a string of bits in one clock tick. l A microoperation is an elementary operation performed on data stored in the datapath. They fall into four general categories: –Transfer microoperations: transfer binary data from one register (or data input/memory) to another. –Arithmetic microoperations: perform arithmetic on data in registers. –Logic microoperations: perform bit manipulations on data in registers. –Shift microoperations: shift data in registers.

34. CEG 360/560 - EE 451/651 Section III - 33 Register-Transfer Level Design l An approach to specify, analyze, and design systems too complex to use the state-table based approaches commonly utilized in “simple” designs. l The Register-Transfer Level (RTL) approach is characterized by: –A digital system is viewed as divided into a data subsystem and a control subsystem. –The state of the data subsystem consists of the contents of the registers. –The function of the system is performed as a sequence of register transfers. –A register transfer is a transformation performed on the datum while the datum is transferred from one register to another. –The sequence of register transfers is controlled by the control subsystem. l The operation of the device can be designed as a sequence of register transfers can be designed using state diagrams, ASM charts, etc. –Each transfer must correspond to a sequence of microoperations. –The control unit implements the RTL design through microoperations.

35. CEG 360/560 - EE 451/651 Section III - 34 RTL Languages (1) l The notation for register transfers are sufficiently complete to describe any digital system at the register-transfer level. –known as register-transfer languages. l Registers are denoted by uppercase letters (sometimes followed by numbers) that indicate the function of the register –e.g. R0, R1, AR, PC, MAR, et al. –The individual bits can be denoted using parenthesis and bit numbers or labels l e.g. R0(0), R0(7:0), PC(L), PC(H) l Data transfer is denoted in symbolic form by the means of the replacement operator . –e.g. R2  R1

36. CEG 360/560 - EE 451/651 Section III - 35 RTL Languages (2) l Normally we want a given transfer to occur not for every clock pulse, but only for specific values of the control signals. –RTL conditional statements: l e.g. If (K1 = 1) Then (R2  R1) –Control function notation (Colon, :) l e.g. K1: R2  R1 l All RTL statements occur in response to a clock tick. A comma is used to separate two or more register transfers that are executed at the same time. A semi-colon is used for an instruction with different control –e.g. Brake: R2  R1, R4  R3; not(Brake): R1  R2

37. CEG 360/560 - EE 451/651 Section III - 36 RTL Languages (3) l Register to Memory Transfers are denoted using square brackets surrounding the memory address. –e.g. DR  M[AR] (Read operation) –e.g. M[AR]  SR (Write operation)

38. CEG 360/560 - EE 451/651 Section III - 37 RTL Languages (4) Examples of Arithmetic Microoperations Examples of Logic Microoperations

39. CEG 360/560 - EE 451/651 Section III - 38 Designing a datapath l Design a device with two 8-bit inputs A and B, one 1-bit input START, one 8-bit output C, and one 1-bit output DONE. The device begins idle (with output DONE = 0). When START is asserted (for one clock tick) the unsigned binary inputs A and B are and held constant until the device asserts “DONE”. The device must calculate the approximate length of the hypotenuse of a right triangle with sides A and B. When the final answer is available on output C, the device will assert DONE for one clock tick. If the answer cannot be computed, assert ERR. A B C C = sqrt (A 2 + B 2 ) START A B DONE C > 8 8 8 ERR

40. CEG 360/560 - EE 451/651 Section III - 39 Designing a datapath l Euler formula for Square Root Approximation: –Let x = max (|a|, |b|) –Let y = min (|a|, |b|) –Sqrt (a^2 + b^2) ~= max (x,(0.875x+0.5y)) l What sort of functions do you need to process the data?

41. CEG 360/560 - EE 451/651 Section III - 40 Designing a datapath l SRA Circuit ModelLet x = max (a, b) and y = min (a, b) –Sqrt (a^2 + b^2) ~= max (x,(0.875x+0.5y)) Datapath Registers: c, x, y, t Functions: min, max, +, -, shift Control unit … Rx  max (A, B) Ry  min (A, B) Ry  Ry >> 1 # shift right 1; *0.5 Rt  Rx >> 3 # shift right 3 (1/8 th ) Rt  Rx – Rt # x – 1/8x = x*0.875 Rt  Ry + Rt Rc  max (Rx, Rt) C  Rc …

42. CEG 360/560 - EE 451/651 Section III - 41 Designing a datapath Control unit … Rx  max (A, B) Ry  min (A, B) Ry  Ry >> 1 Rt  Rx >> 3 Rt  Rx – Rt Rt  Ry + Rt Rc  max (Rx, Rt) C  Rc … RG8 RtLD 8 8 RtIN > Rt RG8 RxLD 8 8 RxIN > Rx RG8 RyLD 8 8 RyIN > Ry RG8 RcLD 8 8 RcIN > Rc 8b-Shifter 8 8 MUX MXS 88 RyRx 01 SR1,3 ALU8 88 8 ALU+- MUX MXA1 88 RyRx 01 Rt 8 MUX MXC2 88 BRt 01 8 MUX MXC1 88 ARx 01 Min Max 88 MUX 0123 MXF 8 RcIN, RxIN, RyIN, RtIN CB A 8 88 2 Overflow C

43. CEG 360/560 - EE 451/651 Section III - 42 Designing a datapath Control unit … Rx  max (A, B) Ry  min (A, B) Ry  Ry >> 1 Rt  Rx >> 3 Rt  Rx – Rt Rt  Ry + Rt Rc  max (Rx, Rt) C  Rc … B A 8 8 Datapath LDRx, LDRy, LDRt, LDRc 4 MXC1, MXC2 2 MXA1, ALU+- 2 MXS, SR1,3 2 MXF 2 C 8 Overflow Control Signals Data Inputs Data Outputs Status Signals

44. CEG 360/560 - EE 451/651 Section III - 43 Outline l Dealing with Complexity l Data unit (Datapath) design –Registers –RTL language –Datapath Construction l Control unit (Controller) design –ASM Charts l Implementation issues –PLDs –ROM –VLSI Design

45. CEG 360/560 - EE 451/651 Section III - 44 Interaction between Data and Control Units l Control Signals - signals that activate data-processing functions. –To activate a sequence of such operations, the control unit sends the proper sequence of control signals to the datapath. l Status Signals - signals that describe aspects of the state of the datapath. –The control unit uses these signals in determining the specific sequence of operations to be performed. l Other Signals - allow the control unit and datapath to interact with other parts of the system, such as memory and input-output logic. Control UnitDatapath Control Signals Status Signals Control Outputs Data Inputs Control Inputs Data Outputs

46. CEG 360/560 - EE 451/651 Section III - 45 The Control Unit l The control unit generates the signals for sequencing the operations in the datapath –A sequential circuit with states that dictate the control signals for the system –Using status conditions and control inputs, the sequential control unit determines the next state in which additional microoperations are activated. l Hardwired Control –The control unit is implemented to provide a particular digital function l Microprogrammed Control –LATER!

47. CEG 360/560 - EE 451/651 Section III - 46 Control Unit Design Control unit Next State StartOverflow = PS 00011011RTL IDLE IDLEIDLES1S1 S1S2S2S2S2Rx  max (A, B) S2S3S3S3S3Ry  min (A, B) S3S4S4S4S4Ry  Ry >> 1 S4S5S5S5S5Rt  Rx >> 3 S5S6S6S6S6Rt  Rx – Rt S6S7ERRS7ERRRt  Ry + Rt S7S8S8S8s8Rc  max (Rx, Rt) S8IDLEIDLEIDLEIDLEC  Rc; Done  1 ERRIDLEIDLEIDLEIDLEERR  1 Start Overflow Done LDx …

48. CEG 360/560 - EE 451/651 Section III - 47 ASM for Control Control unit … Rx  max (A, B) Ry  min (A, B) Ry  Ry >> 1 Rt  Rx >> 3 Rt  Rx – Rt Rt  Ry + Rt Rc  max (Rx, Rt) C  Rc; DONE  1 … Rx  max (A,B) Ry  max (A,B) Ry  Ry >> 1 Rt  Rx >> 3...... LDRx, MXC1=0, MC2=0, MXF=1 LDRy, MXC1=0 MC2=0, MXF=0 LDRy, MXS=0, SR1,3 = 0 LDRt, MXS=1, SR1,3 = 1......

49. CEG 360/560 - EE 451/651 Section III - 48 Algorithmic State Machines l Algorithmic State Machine (ASM) Chart –Special flowchart used to define digital hardware algorithms –Describes a sequence of events –Determines the actions which occur in the states l in response to the clock pulse l in response to changes in the inputs l ASM Charts contain three basic elements: –State boxes l Rectangles, labeled with the state name and assignment, containing a register operation and/or the names of Moore outputs asserted in that state. –Decision boxes l Diamonds containing a conditional input expression and exits 1 and 0. –Conditional output boxes l Ovals containing Mealy outputs asserted for the conditions leading to the box.

50. CEG 360/560 - EE 451/651 Section III - 49 ASM elements Moore output list state namestate code state entry path state exit path State box condition Decision box 01 0 1 OR condition false exit path condition true exit path conditional output list from decision-box exit path Conditional (Mealy) output box

51. CEG 360/560 - EE 451/651 Section III - 50 ASM Timing l Each state box has a corresponding “ASM Block” that includes all decision and conditional output boxes reached from that state –Each ASM Block has exactly one state box, all paths leaving the ASM Block lead directly to a different state box. l The current state box represents the current state. l The current inputs decide a path through the decision boxes. –Unlike state diagrams, ambiguity is easily avoided in ASM charts. –Conditional outputs along the path occur immediately in response to changes in the inputs values. l The next state box is not entered until a clock tick occurs. –The Moore outputs in the state box and any conditional (Mealy) outputs in the new ASM Block are asserted immediately. l ASM boxes may also include Register Transfer directives! –Any changes (conditional or otherwise) to a sequential device wait until the next positive clock edge.

52. CEG 360/560 - EE 451/651 Section III - 51 ASM Example: 4-bit binary counter Z1,Z0 STATE = Q1 Q0 00 01 10 11 A B C D Z0 Z1 Z=3 STATE = Q1 Q0 00 01 10 11 A B C D Z=1 Z=2 -or- Z=0

53. CEG 360/560 - EE 451/651 Section III - 52 ASM Example: 4-bit counter with enable EN STATE = Q1 Q0 A 00 B 01 C 10 D 11 0 1 0 1 0 1 0 1 Z=3 Z=1 Z=0Z=2

54. CEG 360/560 - EE 451/651 Section III - 53 ASM Example: Modulo-4 counter (Mealy) EN A 0001 0 1 C 0100 D 1000 B 0010 EN 0 1 MAX STATE = QD QC QB QA (one hot) Mealy output

55. CEG 360/560 - EE 451/651 Section III - 54 ASM Example: 1’s Counter l Count # of 1’s on X & Y inputs output Z if count = multiple of 4 ( 0, 4, 8... ) If ( X  Y ) 2 1’s( Inc by 2 ) Else if ( X+Y ) 1 1’s( Inc by 1 ) Else 0 1’s( No Inc )

56. CEG 360/560 - EE 451/651 Section III - 55 ASM chart for 1’s Counter XYXY X +Y XYXY XYXY Z XYXY S0 00S1 01S2 10S3 11 1 0 1 0 1 0 1 0 STATE = Q1 Q2 0000 1111 

57. CEG 360/560 - EE 451/651 Section III - 56 Convert ASM chart to Transition List l Needs an extra step to find transition expressions l Trace all possible paths, from any state to all destination states l Transition expression to any given next state (= one line of the transition list) is product (AND) of all conditions along path: l ( condition) if 1 branch taken –(condition)’ if 0 branch taken

58. CEG 360/560 - EE 451/651 Section III - 57 Example: 1’s Counter Z XYXY X +Y S0 00 1 0 0 1 (XY)’(X+Y) (XY) (XY)’(X+Y)’ PSINPUTNS 00(XY)10 00(XY)’(X+Y)01 00(XY)’(X+Y)’00

59. CEG 360/560 - EE 451/651 Section III - 58 Example: 1’s Counter Q1Q0INPUT Q1*Q0* 00(XY)10 00(XY)’(X+Y)01 00(XY)’(X+Y)’00 01(XY)11 01(XY)’(X+Y)10 01(XY)’(X+Y)’01 10(XY)00 10(XY)’(X+Y)11 10(XY)’(X+Y)’10 11(XY)01 11(XY)’(X+Y)00 11(XY)’(X+Y)’11 Q1* = Q1’Q0’(XY) + Q1’Q0(XY) + Q1’Q0(XY)’(X+Y) + Q1Q0’(XY)’(X+Y) + Q1Q0’(XY)’(X+Y)’ + Q1Q0(XY)’(X+Y)’ Q2* = Q1’Q0’(XY)’(X+Y) + Q1’Q0(XY) + Q1’Q0(XY)’(X+Y)’ + Q1Q0’(XY)’(X+Y) + Q1Q0(XY) + Q1Q0(XY)’(X+Y)’ +

60. CEG 360/560 - EE 451/651 Section III - 59 Outline l Dealing with Complexity l Data unit (Datapath) design –Registers –RTL language –Datapath Construction l Control unit (Controller) design –ASM Charts l Implementation issues –PLDs –ROM –VLSI Design

61. CEG 360/560 - EE 451/651 Section III - 60 Programmable Logic Definitions l Digital integrated circuit (MSI, LSI, VLSI) –manufactured as a standard off-the-shelf component –containing “regular” array of logic gates and flip-flops –whose logic functions are determined by the application design engineer and implemented locally l Many types of programmable logic –sometimes generically called PLDs (Programmable Logic Devices) –PAL or PLD –PROM –FPGA output input Combinational PLD

62. CEG 360/560 - EE 451/651 Section III - 61 Programmable Logic Definitions l PLA –Programmable Logic Array –first PLDs –simple programmable AND/OR array –programmed by “blowing fuses” by hand or by mask

63. CEG 360/560 - EE 451/651 Section III - 62 l PAL –Programmable Array Logic –similar to a PLA, but the OR- array is fixed –most commonly used PLD –may include input/output flip- flops l GAL –Generic Array Logic –can be configured to emulate the AND/OR, flip-flop, and output structure of a variety of combinational and sequential PAL devices Programmable Logic

64. CEG 360/560 - EE 451/651 Section III - 63 Read-Only Memory (ROM) l A combinational circuit with n inputs and b outputs: 2 n x b ROM Address inputs A(n-1,..., 0) nb Data outputs D(b-1,..., 0) Programmable  values determined by user Nonvolatile  contents retained without power Uniform (Random) Access  delay is uniform for all addresses

65. CEG 360/560 - EE 451/651 Section III - 64 Read-Only Memory (ROM) l Two views: –ROM stores 2 n words of b bits each, or –ROM stores an n-input, b-output truth table Example: A1 A0 D3 D2 D1 D0 0 0 0 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 Stores 4 4-bit words, or stores 4 functions of 2 input variables b = 4 n = 2

66. CEG 360/560 - EE 451/651 Section III - 65 Using ROMs for Combinational Logic A 3-input, 4-output combinational logic function: Function: 2-to-4 Decoder with Polarity Control A2 = Polarity (0 = active Low, 1= active High) A1, A0 = I1, I0 (2-bit input ) D3...D0 = Y3...Y0 (4-bit decoded output) Inputs Outputs A2 A1 A0 D3 D2 D1 D0 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 8  ROM A0 D0 A1 D1 A2 D2 D3 Y0 I1 POL Y1 Y2 Y3 I0

67. CEG 360/560 - EE 451/651 Section III - 66 Internal Structure of 4 Internal Structure of 4  Diode ROM D0 D1 D2 D3 2 to 4 Decoder A1 A0 Bit Lines /w0 /w1 /w2 /w3 Diode 1 No Diode 0 0101 0001 1000 1111 1 of n Word Lines R0R1R2R3 +5 V Why use diodes? Why not replace them with wires?

68. CEG 360/560 - EE 451/651 Section III - 67 Types Of ROMs (1) l Mask ROM –Connections made by the semiconductor vendor –Expensive setup cost –Several weeks for delivery –High volume only –Bipolar or MOS technology l PROM –Programmable ROM –Connections made by equipment manufacturer –Vaporize (blow) fusible links with PROM programmer using high voltage/current pulses –Bipolar technology –One-time programmable Word Line Bit Line

69. CEG 360/560 - EE 451/651 Section III - 68 Internal Structure of Transistor ROM R0R1R2R3 +5 V /D3 /D2 /D1 /D0 Transistor 1 No transistor 0 w3 l Replace diodes with MOS transistors l Change decoder to active-high outputs 1000

70. CEG 360/560 - EE 451/651 Section III - 69 EPROM and EEPROM Structure VDDVDD Floating gate Nonfloating gate Active-high word lines Active-low bit lines

71. CEG 360/560 - EE 451/651 Section III - 70 Types of ROMs (2) l EPROM –Erasable Programmable ROM –Charge trapped on extra “floating gate” of MOS transistors –Exposure to UV light removes charge l 10-20 minutes l Quartz Lid = expensive package –Limited number of erasures (10-100) l EEPROM (E 2 ROM) –Electrically Erasable ROM –Floating gates charged/discharged electrically –Not RAM! (relatively slow charge/discharge) –limited number of charge/discharge cycles (10,000) Word Line Bit Line

72. CEG 360/560 - EE 451/651 Section III - 71 Types of ROMs (3) l Flash Memory –Electronically erasable in blocks –100,000 erase cycles –Simpler and denser than EEPROM –Often used for firmware

73. CEG 360/560 - EE 451/651 Section III - 72 ROM Type Summary Type Mask ROM PROM EPROM EEPROM FLASH Technology NMOS, CMOS Bipolar NMOS, CMOS NMOS CMOS Read Cycle 20-200 ns <100 ns 25-200 ns 50-200 ns 25-200 ns Write Cycle 4 weeks 5 minutes 10  s/byte 10  s/block Comments Write once; low power Write once; high power; low density Write once; high power; no mask charge Reusable; low power; no mask charge 10,000 writes/location limit 100,000 erase cycles

74. CEG 360/560 - EE 451/651 Section III - 73 Consider a 64 x 1 ROM Very tall, narrow chip (BAD) Even worse for larger chips! How can we make it more square? This Decoder needs 64 6-input gates! +5 V 6-to-64 Decoder /w0 /w1 /w63 A5 A0    64 x 1 Diode Array D0

75. CEG 360/560 - EE 451/651 Section III - 74 64 x 1 ROM with 2-Dimensional Decoding Almost square chip! 3 to 8 Decoder /w0 /w1 /w7 +5 V 0 7 8 to 1 mux A5 A3 A2 A0 D0     Decoder and mux = 8 3-input gates + 8 4-input gates 8 x 8 Diode Array

76. CEG 360/560 - EE 451/651 Section III - 75 64K x 8 ROM with 2-D Decoding 9 to 512 Decoder A A   512  128 to 1 Mux   D0D1D7 512  128 512  128 512  1024 Array 128 to 1 Mux 128 to 1 Mux 128 Is this a square chip? 2-D Decoding / Coincident selection 64k x 8 = 2 16 * 2 3 = 2 19 square root (2 19 ) ~= 2 9

77. CEG 360/560 - EE 451/651 Section III - 76 Internal 2 n x b ROM Control Structure Row decoder Power on Storage array Column multiplexer A0 A1 A m-1 AmAm A m+1 A n-1 /CS /OE Db-1Db-2D0 Power on Power on

78. CEG 360/560 - EE 451/651 Section III - 77 Programmable Logic l Advantages –Design flexibility –Better design automation –Higher density, fewer packages (compared to SSI-MSI) –Less expensive –Lower power –Higher performance l Programming Technologies –Interconnections usually made by pass transistors controlled by memory bits of some type: –Antifuse - permanent connections made electrically –EPROM - charged floating gate, UV erasable –EEPROM - charged floating gate, electrically erasable –Flash Memory - charged floating gate, electrically erasable –Programmed using CAD - Hardware Description Languages

79. CEG 360/560 - EE 451/651 Section III - 78 Modern (VLSI) Design l The VLSI chips that are used in most modern designs come in three varieties: –Custom Approach: VLSI chips, or some of their parts, are designed by hand. l Full Custom Vs. Standard Cell - Using standard cell designs (same height, variable width) and routing channels simplifies the design process l Highest Density, Highest Manufacturing Cost –Semicustom Approach: The VLSI chips employ gate arrays and technology mapping. l Gate array: a partially prefabricated IC that incorporates a large number of identical gates (usually 3-input NAND or NOR gates) that are laid out in a regular two-dimensional array. l Technology mapping: The process of designing a logic function as a network of available devices. l Lower Density (10-25% more gates than an equivalent custom design). l Inexpensive: Requires only metal deposition (define interconnections), economy of scale.

80. CEG 360/560 - EE 451/651 Section III - 79 Modern (VLSI) Design l The VLSI chips that are used in most modern designs come in three varieties: –VLSI PLDs l Field Programmable Gate Arrays (FPGAs) l A VLSI modules that can be programmed to implement a digital system consisting of tens of thousands of gates. l LSI PLDs implement two-level combinational and sequential networks, l FPGAs allow the realization of multilevel networks and complex systems on a single chip! l Highly reprogrammable! l Low cost l May produce slower network l May require a larger silicon area