1. M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June 2003 1 Rad-Hard qualification for the LHCb RICH L0 electronics M. Adinolfi University of Oxford

2. M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June 2003 2 The problem There are 3 main type of radiation effects to take into account: Total Ionising Dose we expect of the order of 2 krad per year (includes a safety factor of 2 in the simulation) Displacement damage - atoms in the lattice are displaced by collisions with hadrons. Bipolar and optical devices are particularly sensible to this. Single Event Effects i.e. effects which are not cumulative

3. M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June 2003 3 Single Event Upsets  The circuit is designed so that it has two stable states, one that represents a stored '0' and one that represents a stored '1.' In each state, two transistors are turned on and two are turned off. A bit-flip occurs when an energetic particle causes the state of the transistors in the circuit to reverse. This phenomenon occurs in many microcircuits, including memory chips and microprocessors.  The particle produces charges along its path, in the form of electrons and holes. These are collected at the source and drain, and a current pulse appears. This can be large enough to produce an effect like that of a normal signal applied to the transistor.

4. M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June 2003 4 Single Event Latchup  Circuits are manually made in silicon by combining adjacent p-type and n-type regions into transistors.  Paths other than those chosen to form the desired transistor can sometimes result in so-called parasitic transistors, which, under normal conditions, cannot be activated.  Latchup occurs when a spurious current spike, such as that produced by a heavy cosmic ray, activates one of a pair of these parasitic transistors, which combine into a circuit with large positive feedback.  The result is that the circuit turns fully on and causes a short across the device until the latter burns up or the power to it is cycled.

5. M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June 2003 5 What do we know of the components? Some results are available on the web (e.g. see http://klabs.org) but:  Although the published test have been made by employees of the producer they are not official results shown in components specs.  These are presentations on web, they are not articles published on refereed magazines.  They can be used as guideline but need verification. SEU cross section for AX series SRAM

6. M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June 2003 6 How does this affect the L0 FE Electronic components in the L0 board which may be sensitive to radiation effects include: Flash ADC. VICSEL. The beetle packaging if not in ceramics. FPGA. In particular FPGA can have SEU in different parts of its circuitry including the Program, the RAM, the Registers. In general the cross-section will be different in the different parts. All of them need to be verified. The effects of SEU in the program can be minimized by using anti-fuse technology e.g. the ACTEL AX family. Anti-fuse devices are vulnerable to another effect: Single Event Dielectric Rupture in which an anti-fuse connection in the chip is broken. In general producers do not quote SEU rates. Chips which are qualified can be purchased but the cost is of the order of $1000 per chip! LHCb qualification program appears to be the only way.

7. M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June 2003 7 The tests of an FPGA: example  See ESA_QCA0109TS_C project.  14 pipelined shift registers each 144 bit long is implemented together with self-test circuitry.  Data is compared with itself and any mismatch is reported.  Data is generated by a feed back flip-flop register and an external clock.

8. M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June 2003 8 The tests of an FPGA: example (2)  Triple redundancy logic can be used to minimize the effect of SEU.  SEU rates needs measuring in this case too.

9. M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June 2003 9 Testing or reinventing the wheel  Several labs in LHCb are interested in radiation verification. Tests for components such as the ADC and the VICSEL can probably be shared.  Only other detector interested in the ACTEL is the calorimeter. The dose in the ECAL electronics is ~10 time less than in RICH-1. ECAL has not scheduled any test.  In principle it’d be ideal to test components on a board as close as possible to the final version. This would allow test the FPGA algorithms and would avoid working on different DAQ, monitoring etc systems.  Radiation qualification tests need to be done as soon as possible.  Only viable solution seems to be to develop a simple board hosting the components to be tested, with a simple DAQ connected.

10. M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June 2003 10 What do we need? In order to test the FPGA within a few months we need: A custom made board to host the FPGA and eventually the other components. A DAQ system: the L1 board with minimal configuration and a laptop can be used. This is possibly no longer true if the ADC and the VICSEL are also being tested. Special monitoring facilities for example for the current - possibly this needs to be done also in the experiment. If the PINT algorithm is to be used to test it a TTC system is also needed. This is not required if we’re happy with a test based on a shift register. The whole system is to be fully functional, easily transportable, plug-and-play, fast to use. Beam or nuclear sources cost money! Ideally more than 1 FPGA (  2) should be tested. Somebody to do it!