1. Proposal for read-out of Forward Detector straw tubes PANDA DAT requirements General layout Prototypes M. Idzik, M. Kajetanowicz, K.Korcyl, G. Korcyl, H.Kuc, A. Misiak, P.Salabura, J. Smyrski, R. Trębacz Krakow Panda group

2. Straw tubes read-out chain FE cards (preamp+ shaper+ discriminator) Sensitivity ~ 3 fC, noise <1 fC based on available ASIC's : CARIOCA or new development based on LUMICAL++ (Marek Idzik) located on detector frames differential output (LVDS) Trigger and Read-our Boards- TRB based on HTDC : time measurement + TimeOverThreshold for amplidtude meas. time w.r.t external common clock, 780 ps binning (low resolution-40 MHz clock) Zero suppression & Hit detection. Slow control interface (i.e EPICS) data output via GBit optical link Common Clock Distribution Detector Concentrator : Compute Node ATCA standard several TRB inputs Detector memory buffer feature extraction –cluster and tracklet finding i.e based on fired wires numbers and time stamps FE TRB Detector Concentrator Straws: ~ 15000 tubes (6 chambers*8 planes) Max drift time ~ 150 ns, @ 500 kHz max averaged hit rate pile up <10%, 2-3 ns time resolution Gain: ~ 2 * 10 4 Ar (90)/CO 2 (10) mixture

3. FEE Connection to detector Z det (f)  (f >50 MHz)  L/C=370  C det = 9pF/m (14-18 pF) NEED LOT OF ATTENTION !!!! ? (not decided, yet) CARIOCA ?

4. FEE cards should be electr. shielded ! FEE (LUMICAL) connected to straws (UJ october 2008) FEE Connection to detector additional resis. ?

5. CARIOCA 10 CARIOCA (IBM 0.25  m CMOS6SF ): 8 channels, preamp, shaper, BLR, discriminator, differential (LVDS) output: radiation hardness (checked for LHC requirements: no effects up to 20 Mrad dose) Sensitivity : at 220 pF for negative pulse : 2.3 mV/fC peaking time 14 ns, pulse width 60 ns power consumption 25 mW/channel 4 ASIC FEE-UJ’2008 CERN -proto

6. Characteristic (I): amplitude as a function of injected charge : CARIOCA 10 gain ~ 2,6 mV/fC TR TD TF

8. Carioca+Straw tube (TOT) HV: 1500 V HV: 1400 V no source Sr 90 source Noise (external pick-up) ~ 8 fC (status last year) – not satisfactory New FEE board (better grounding) + em. shielding expected to improve situation

9. Time Over Threshold – energy loss HADES MDC Signal height (V) ~ dE/dxdE/dx vs momentum Jochen Markert, A.Schmah (GSI) 24 * ~7 mm gaps He:Iso (2:1) FEE based on ASD8 chip

10. Time Over Threshold – energy loss resolution measured by HADES MDC

11. Garfield simulations for straws Pions 0.8 GeV/c Protons 0.8 GeV/c one strawaverage from 20 straws Ar:CO 2 (90:10) @ 2 bars HV 1500 V charge integration time 100 ns perpendicular incidence  ~5-6%

12. AddOn connector Trigger and Read-out Board developed in synergy with HADES experiment 128 channel TDC based on HPTDC optional On-board DAQ functionality via ETRAX- FS (LINUX OS 3 200 MHz processors: 100MBit/s Fast Ethernet interface) Optical Digital link 2GBit/s) High speed (15 Gb/s) AddOn-connector (32 LVDS) DSP (TigerSharc TS201) for on-line trigger algorithms/ pre-processing LVDSTTL Virtex4 (LX40) EtraxFS SDRAM 2GBit/s optical link DSP (TS201) Optional SDRAM 100MBit/s ethernet HPTDCHPTDCHPTDCHPTDC

13. Marek Palka, GSI13 The TRBv2 DC/DC ETRAX DSP FPGAVirtex4 TDC 0, 1 TDC 2, 3 SDRAM Optical link SDRAM Ethernet 4 TDC – 128 channels (~40ps RMS resolution) FPGA – Virtex4LX40 4x512Mb SDRAM ETRAX FS 100Mb/s,TCP/IP 2,5 Gb/s optical link DSP TigerSharc AddOn connector DC/DC converters

14. HUB 12 TRB Conversion from 2 Gb/s 8/10 bit serial transmission to Ethernet protocol (UDP) 16 SFPs (Small Form-factor Pluggable transceivers) optical connectors receive/transmit: ie 12 * 2Gb/s and 4 * 1Gb Ethernet FPGA (Lattice SCM 25) with IP core Conversion to Ethernet tested (G. Korcyl)

15. Expected rates p beam = 15 GeV/c, N Int =2x10 7 s -1.

16. HPTDC working mode with free running clock 1 MHz trigger clock 1  s matching window (1,2  s searching window) (T.latency=match.window) Multiplicty of hit/channel  0.4 (in window) by 400 kHz /wire hit losses neglegible (concern for >3 MHz/channel) TDC data: leading & trailing edge : 32 bits(header: TDC id, Event ID, Bunch Id) 32 bits data : TDC id, channel, data 19 bits (pairing mode: 12 bits trailing + 7 bits width) 32 bits(trailer) clock (1MHz) time match. window T

17. Data flow estimate (example) 128 channels/wire plane :4 FEE(32 channels each) - 1 TRB card (4x32 channels HPTDC) 2.0 Gbit/s link (250 MByte/s )- total max load (4 links) =1.0 GByte/s average maximal load/TRB (1 HPTDC): 13 MHit/s ( 13 hits per trigger/TDC) @ 400 kHz rate/wire 13 MHits*10 Bytes(hit=trailing + falling edge) = 130 MByte/s x 8 (wire planes) FEE TRB 4 links (1 GByte/s) to Compute Nodes wire plane O degree plane Left (L) O degree plane Right (R)

18. back-up slides

19. Characteristics : Amplitude as a function of injected charge: LumiCal (AGH) ASIC gain ~ 13 mV/fC

20. Pulses from detector in LUMIVAL (Rf mode) X- ray source 55 Fe HV = 1200 VHV = 1350 V Pulses from iron source 55 Fe, in gas mixture 90 % Ar 10 % CO 2 Visible differences between pulses from escape peak and main peak, At picture on the right side pulses saturation of large pulses is visible shape changes because of amplitude saturation after X-ray escape full absorption

21. Cosmic rays: straw tube with LumiCal chip and ADC with gate signal from scintillating detector HV = 1300 V, gas mixture 90 % Ar 10 % CO 2 noise peak, generated because of larger scintillator area as compared to straw tube

22. Detector and DAT requirements interaction rate: 20 MHz raw data flow: 40 - 80 GB/s typ. event size: 4 – 8 kB lack of ONE SPECIFIC hardware trigger signal continuously sampling FE (time stamps) flexibility in the choice of triggering algorithms

23. PANDA DAT architecture (one possible choice) 2 alternative options considered so far (K. Korcyl ) 1.push and pull 2.„push only”

24. 24 The HADES DAQ (>100 TRBs!) CTS... TRB for RPC TRB + MDC AddOn TRB + RICH AddOn TRB + Shower AddOn LVL1 Trigger box TRB for Time Wall,Start,Veto TRB + TOF AddOn Parallel Event Building (computers) Ethernet to the front end electronics TRB + HUB AddOn TRB + General purpose AddOn TRBnet VME CPU

25. HPTDC features Used in many HEP experiments. Developed at CERN, produced in IBM technology 0.25  m CMOS (ibm) 32 channels multihit TDC with variable resolution: 785ps, 195ps, 98ps, 25ps (LSB) - measurement wrt. free running clock, self calibration, double pulse resolution typ. 5 ns Max hit rate/channel 2 MHz, Trigger rates up to 1MHz @40MHz clock Internal buffer to story hits (max 256 hits/8 channel)- buffer BUT with 4 deep derandomizer in each channel individual registration of leading and trailing edges inside internal chip buffers- Time over Threshold Two operation modes: A: TRIGGER MATCHING disabled. The raw time measurements from input channels are passed unchanged to the read-out fifo and can be readout to external buffers. 40 MHz read-out B. TRIGGER MATCHING enabled. Hits inside pre-programmed window are filtered. Latencies <50  s High rates->low latencies

27. HPTDC hit losses 25 ns dead time reduces loss by factor 10 at 3 MHz rate hit rate